LPP » INSTRU » VHDLib

{{child_pages}}

{{collapse(View details...)

This is a block of text that is collapsed by default.

It can be expanded by clicking a link.

}}

----

<pre><code class="C++">

  GENERIC (

    NB_FF_OF_SYNC : INTEGER := 2);

  PORT (

    clk    : IN  STD_LOGIC;

    rstn   : IN  STD_LOGIC;

    A      : IN  STD_LOGIC;

    A_sync : OUT STD_LOGIC);

</code></pre>

h1. IP documentation

h2. General Purpose

----

h3. Synchronizer

{{collapse(SyncFF)

!{width: 20%}SYNC_FF.png! 

|_.Signal      |_.Type         |_.Size  |_.Function            |_. Active   |

|clk           |input          |1       |clock                 |rising edge |

|rstn          |input          |1       |reset                 |low         |

|A             |input          |1       |data in               |            |

|A_sync        |ouput          |1       |data out synchronized |            |

}}

{{include(https://hephaistos.lpp.polytechnique.fr/rhodecode/HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib/files/bf3115c7b73fabc361d1693b36a643a1f87c8897/lib/staging/LPP/JCP/general_purpose/Synchronizer/SYNC_FF.vhd)}}