IP documentation » History » Version 37
Jean-Christophe Pellion, 28/02/2014 03:41 PM
1 | 10 | Jean-Christophe Pellion | {{>toc}} |
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2 | 1 | Jean-Christophe Pellion | |
3 | 11 | Jean-Christophe Pellion | h1. IP Documentation |
4 | 1 | Jean-Christophe Pellion | |
5 | 15 | Jean-Christophe Pellion | ---- |
6 | |||
7 | 36 | Jean-Christophe Pellion | h2. Sample Type |
8 | |||
9 | {{collapse(Sample Type) |
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10 | |||
11 | <pre><code class="vhdl"> |
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12 | |||
13 | |||
14 | TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0); |
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15 | |||
16 | SUBTYPE Samples24 IS STD_LOGIC_VECTOR(23 DOWNTO 0); |
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17 | SUBTYPE Samples16 IS STD_LOGIC_VECTOR(15 DOWNTO 0); |
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18 | SUBTYPE Samples14 IS STD_LOGIC_VECTOR(13 DOWNTO 0); |
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19 | SUBTYPE Samples12 IS STD_LOGIC_VECTOR(11 DOWNTO 0); |
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20 | SUBTYPE Samples10 IS STD_LOGIC_VECTOR( 9 DOWNTO 0); |
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21 | SUBTYPE Samples8 IS STD_LOGIC_VECTOR( 7 DOWNTO 0); |
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22 | |||
23 | TYPE Samples24v IS ARRAY(NATURAL RANGE <>) OF Samples24; |
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24 | TYPE Samples16v IS ARRAY(NATURAL RANGE <>) OF Samples16; |
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25 | TYPE Samples14v IS ARRAY(NATURAL RANGE <>) OF Samples14; |
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26 | TYPE Samples12v IS ARRAY(NATURAL RANGE <>) OF Samples12; |
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27 | TYPE Samples10v IS ARRAY(NATURAL RANGE <>) OF Samples10; |
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28 | TYPE Samples8v IS ARRAY(NATURAL RANGE <>) OF Samples8; |
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29 | </code></pre> |
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30 | }} |
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31 | |||
32 | ---- |
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33 | |||
34 | 11 | Jean-Christophe Pellion | h2. General Purpose |
35 | 1 | Jean-Christophe Pellion | |
36 | 15 | Jean-Christophe Pellion | h3. Edge Detection |
37 | 1 | Jean-Christophe Pellion | |
38 | 15 | Jean-Christophe Pellion | {{collapse(Edge_Detection) |
39 | EdgeDetection permit to detect the edge of the sin signal. |
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40 | |||
41 | p=. !{width: 20%}edge_detection.png! |
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42 | |||
43 | <pre><code class="vhdl"> |
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44 | COMPONENT lpp_edge_detection |
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45 | PORT ( |
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46 | clk : IN STD_LOGIC; |
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47 | rstn : IN STD_LOGIC; |
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48 | sin : IN STD_LOGIC; |
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49 | sout : OUT STD_LOGIC); |
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50 | END COMPONENT; |
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51 | </code></pre> |
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52 | |||
53 | |_.Signal |_.Direction |_.Size |_.Function |_. Active | |
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54 | |clk |input |1 |clock domain 1 |rising edge | |
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55 | |rstn |input |1 |reset |low | |
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56 | |sin |input |1 |signal in | | |
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57 | |sout |ouput |1 |signal out | | |
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58 | |||
59 | }} |
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60 | {{collapse(Edge_to_level) |
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61 | 20 | Jean-Christophe Pellion | EdgeToLevel permit to transform the positive edge information into a level information. |
62 | 15 | Jean-Christophe Pellion | |
63 | 16 | Jean-Christophe Pellion | p=. !{width: 20%}edge_to_level.png! |
64 | 15 | Jean-Christophe Pellion | |
65 | <pre><code class="vhdl"> |
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66 | 17 | Jean-Christophe Pellion | COMPONENT lpp_edge_to_level |
67 | 15 | Jean-Christophe Pellion | PORT ( |
68 | clk : IN STD_LOGIC; |
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69 | rstn : IN STD_LOGIC; |
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70 | sin : IN STD_LOGIC; |
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71 | sout : OUT STD_LOGIC); |
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72 | END COMPONENT; |
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73 | </code></pre> |
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74 | |||
75 | |_.Signal |_.Direction |_.Size |_.Function |_. Active | |
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76 | |clk |input |1 |clock domain 1 |rising edge | |
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77 | |rstn |input |1 |reset |low | |
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78 | |sin |input |1 |signal in | | |
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79 | |sout |ouput |1 |signal out | | |
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80 | |||
81 | }} |
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82 | |||
83 | 13 | Jean-Christophe Pellion | h3. Synchronizer |
84 | 8 | Jean-Christophe Pellion | |
85 | {{collapse(SYNC_FF) |
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86 | 19 | Jean-Christophe Pellion | Sync_FF permit to synchronize a signal A in the clock domain clk. Normally, A signal should be the output of a FF cloked in an other domain. You shouldtn't have "logic" between the 2 domain. |
87 | You can configure the number FF use to synchronize (NB_FF_OF_SYNC). This number is depending of the MTBF(Mean Time Between Failure). |
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88 | 13 | Jean-Christophe Pellion | |
89 | p=. !{width: 15%}SYNC_FF.png! |
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90 | 8 | Jean-Christophe Pellion | |
91 | <pre><code class="vhdl"> |
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92 | COMPONENT SYNC_FF_LPP_JCP |
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93 | GENERIC ( |
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94 | NB_FF_OF_SYNC : INTEGER); |
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95 | PORT ( |
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96 | clk : IN STD_LOGIC; |
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97 | rstn : IN STD_LOGIC; |
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98 | A : IN STD_LOGIC; |
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99 | A_sync : OUT STD_LOGIC); |
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100 | END COMPONENT; |
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101 | </code></pre> |
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102 | |||
103 | |_.Parameter |_.Type |_.Size |_.Description |_.Default | |
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104 | 7 | Jean-Christophe Pellion | |NB_FF_OF_SYNC |Integer | |Number of FF |2 | |
105 | 1 | Jean-Christophe Pellion | |\5.| |
106 | |_.Signal |_.Direction |_.Size |_.Function |_. Active | |
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107 | |clk |input |1 |clock |rising edge | |
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108 | |rstn |input |1 |reset |low | |
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109 | 15 | Jean-Christophe Pellion | |sin |input |1 |signal in | | |
110 | |sout |ouput |1 |signal synchronized | | |
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111 | 13 | Jean-Christophe Pellion | |
112 | }} |
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113 | |||
114 | 1 | Jean-Christophe Pellion | {{collapse(SYNC_VALID_BIT) |
115 | 14 | Jean-Christophe Pellion | SYNC_VALID_BIT permit to synchronize a signal of validity from clock domain clk_in to clock domain clk_out. A validity bit is a signal set "high" only one cycle and zero others. To Synchronize this type of signal, a first stage detect the positive edge, a second synchronizes this signal, and a last transform the edge information to a validity bit. |
116 | 19 | Jean-Christophe Pellion | You can configure the FF number of the second stage (NB_FF_OF_SYNC). |
117 | 14 | Jean-Christophe Pellion | |
118 | 13 | Jean-Christophe Pellion | p=. !{width: 20%}SYNC_VALID_BIT.png! |
119 | |||
120 | <pre><code class="vhdl"> |
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121 | COMPONENT SYNC_VALID_BIT_LPP_JCP |
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122 | GENERIC ( |
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123 | NB_FF_OF_SYNC : INTEGER); |
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124 | PORT ( |
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125 | clk_in : IN STD_LOGIC; |
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126 | clk_out : IN STD_LOGIC; |
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127 | rstn : IN STD_LOGIC; |
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128 | sin : IN STD_LOGIC; |
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129 | sout : OUT STD_LOGIC); |
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130 | END COMPONENT; |
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131 | </code></pre> |
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132 | |||
133 | |_.Parameter |_.Type |_.Size |_.Description |_.Default | |
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134 | 1 | Jean-Christophe Pellion | |NB_FF_OF_SYNC |Integer | |Number of FF |2 | |
135 | 13 | Jean-Christophe Pellion | |\5.| |
136 | 18 | Jean-Christophe Pellion | |_.Signal |_.Direction |_.Size |_.Function |_. Active | |
137 | |clk_in |input |1 |clock domain 1 |rising edge | |
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138 | |clk_out |input |1 |clock domain 1 |rising edge | |
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139 | |rstn |input |1 |reset |low | |
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140 | |sin |input |1 |valid bit clocked in domain 1| | |
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141 | |sout |output |1 |valid bit clocked in domain 2| | |
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142 | 2 | Jean-Christophe Pellion | |
143 | }} |
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144 | 21 | Jean-Christophe Pellion | |
145 | ---- |
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146 | |||
147 | h2. SoC (System On Chip) |
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148 | |||
149 | {{collapse(Leon3_Soc) |
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150 | Leon3_SoC is an IP which integrate all the basic IP for using a Leon3 System. This System is configurable : |
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151 | * activate the DSU, AHB uart, APB UART, IRQ manager and timer manager |
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152 | * activate the FPU and select the type of IP using for (netlist or rtl) |
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153 | |||
154 | 23 | Jean-Christophe Pellion | You can connect easily external AMBA IP. For example, if you have only one Leon3 and you want to add an AHB Master My_AHB_MST. You set NB_AHB_MASTER to 1 and connect My_AHB_MST_ahbmi signal to the input ahbi_m_ext and My_AHB_MST_ahbmo to ahbo_m_ext(1). |
155 | 21 | Jean-Christophe Pellion | |
156 | 24 | Jean-Christophe Pellion | |
157 | |_.Number |_.NAME |_.Enable Parameter |_.Address |_.IRQ| |
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158 | |\5=.AHB Master | |
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159 | | 0 to NCPU-1 |leon3s | ||| |
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160 | | NCPU+NB_AHBMASTER |ahbuart |ENABLE_AHB_UART ||| |
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161 | |\5.| |
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162 | |\5=.AHB Slave | |
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163 | | 0 |mctrl | |0x00000000 | | |
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164 | | 1 |apbctrl | |0x80000000 | | |
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165 | | 2 |dsu3 |ENABLE_DSU |0x90000000 |0 | |
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166 | |\5.| |
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167 | |\5=.APB Slave | |
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168 | | 0 |mctrl | |0x80000000 | | |
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169 | | 1 |apbuart |ENABLE_APB_UART |0x80000100 |2 | |
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170 | | 2 |irqmp |ENABLE_IRQMP |0x80000200 | | |
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171 | | 3 |gptimer |ENABLE_GPT |0x80000300 |8 | |
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172 | | 4 |ahbuart |ENABLE_APB_UART |0x80000400 | | |
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173 | |||
174 | 28 | Jean-Christophe Pellion | p=. !{width: 40%}leon3_SoC.png! |
175 | 25 | Jean-Christophe Pellion | |
176 | 21 | Jean-Christophe Pellion | <pre><code class="vhdl"> |
177 | COMPONENT leon3_soc_LPP_JCP |
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178 | GENERIC ( |
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179 | fabtech : INTEGER; |
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180 | memtech : INTEGER; |
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181 | padtech : INTEGER; |
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182 | clktech : INTEGER; |
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183 | disas : INTEGER; |
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184 | dbguart : INTEGER; |
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185 | pclow : INTEGER; |
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186 | clk_freq : INTEGER; |
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187 | NB_CPU : INTEGER; |
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188 | ENABLE_FPU : INTEGER; |
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189 | FPU_NETLIST : INTEGER; |
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190 | ENABLE_DSU : INTEGER; |
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191 | ENABLE_AHB_UART : INTEGER; |
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192 | ENABLE_APB_UART : INTEGER; |
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193 | ENABLE_IRQMP : INTEGER; |
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194 | ENABLE_GPT : INTEGER; |
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195 | NB_AHB_MASTER : INTEGER; |
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196 | NB_AHB_SLAVE : INTEGER; |
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197 | NB_APB_SLAVE : INTEGER); |
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198 | PORT ( |
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199 | clk : IN STD_ULOGIC; |
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200 | rstn : IN STD_ULOGIC; |
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201 | errorn : OUT STD_ULOGIC; |
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202 | ahbrxd : IN STD_ULOGIC; |
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203 | ahbtxd : OUT STD_ULOGIC; |
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204 | urxd1 : IN STD_ULOGIC; |
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205 | utxd1 : OUT STD_ULOGIC; |
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206 | address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); |
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207 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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208 | nSRAM_BE0 : OUT STD_LOGIC; |
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209 | nSRAM_BE1 : OUT STD_LOGIC; |
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210 | nSRAM_BE2 : OUT STD_LOGIC; |
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211 | nSRAM_BE3 : OUT STD_LOGIC; |
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212 | nSRAM_WE : OUT STD_LOGIC; |
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213 | nSRAM_CE : OUT STD_LOGIC; |
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214 | nSRAM_OE : OUT STD_LOGIC; |
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215 | apbi_ext : OUT apb_slv_in_type; |
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216 | apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); |
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217 | ahbi_s_ext : OUT ahb_slv_in_type; |
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218 | ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); |
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219 | ahbi_m_ext : OUT AHB_Mst_In_Type; |
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220 | ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)); |
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221 | END COMPONENT; |
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222 | </code></pre> |
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223 | |||
224 | |_.Parameter |_.Type |_.Size |_.Description |_.Default | |
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225 | |fabtech | INTEGER | |Target technologie |apa3e | |
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226 | |memtech | INTEGER | |Memory Target technologie |apa3e | |
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227 | |padtech | INTEGER | |Pad Target technologie |inferred | |
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228 | |clktech | INTEGER | |Clock target technologie |inferred | |
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229 | |disas | INTEGER | |Activate the disassembler |0 | |
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230 | |dbguart | INTEGER | |Activate debug uart |0 | |
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231 | |pclow | INTEGER | | |2 | |
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232 | |clk_freq | INTEGER | |Clock input frequency (in kHz) |25000 | |
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233 | |NB_CPU | INTEGER | |Number of Leon3 |1 | |
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234 | |ENABLE_FPU | INTEGER | |Enable the FPU |1 | |
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235 | |FPU_NETLIST | INTEGER | |Select the FPU Used (1=> NetList, 0=> RTL) |1 | |
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236 | |ENABLE_DSU | INTEGER | |Enable the Debug System Unit |1 | |
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237 | |ENABLE_AHB_UART | INTEGER | |Enable AHB UART |1 | |
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238 | |ENABLE_APB_UART | INTEGER | |Enable APB UART |1 | |
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239 | |ENABLE_IRQMP | INTEGER | |Enable irq manager |1 | |
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240 | |ENABLE_GPT | INTEGER | |Enable the timer |1 | |
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241 | |NB_AHB_MASTER | INTEGER | |Number of AHB Master outside the SoC |0 | |
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242 | |NB_AHB_SLAVE | INTEGER | |Number of AHB Slave outside the SoC |0 | |
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243 | |NB_APB_SLAVE | INTEGER | |Number of APB Slave outside the SoC |0 | |
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244 | |\5.| |
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245 | |_.Signal |_.Direction |_.Size or Type |_.Function |_. Active | |
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246 | |clk | input |1 |clock |rising edge | |
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247 | |rstn | input |1 |reset |low | |
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248 | |errorn | output |1 |leon 3 error signal | | |
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249 | |ahbrxd | input |1 |AHB uart Rx Signal | | |
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250 | |ahbtxd | output |1 |AHB uart Tx Signal | | |
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251 | |urxd1 | input |1 |APB uart Rx Signal | | |
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252 | |utxd1 | output |1 |APB uart Tx Signal | | |
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253 | |address | output |20 |SRam Address | | |
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254 | |data | inout |32 |SRam Data | | |
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255 | |nSRAM_BE0 | output |1 |SRam bankEnable 0 | | |
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256 | |nSRAM_BE1 | output |1 |SRam bankEnable 1 | | |
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257 | |nSRAM_BE2 | output |1 |SRam bankEnable 2 | | |
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258 | |nSRAM_BE3 | output |1 |SRam bankEnable 3 | | |
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259 | |nSRAM_WE | output |1 |SRam WriteEnable | | |
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260 | |nSRAM_CE | output |1 |SRam ChipEnable | | |
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261 | |nSRAM_OE | output |1 |SRam OutputEnable | | |
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262 | |apbi_ext | output |apb_slv_in_type|APB Slave bus input signal | | |
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263 | |apbo_ext | input |NB_APB_SLAVE of apb_slv_out_type|APB Slave bus output signal | | |
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264 | |ahbi_s_ext | output |ahb_slv_in_type|AHB Slave bus input signal | | |
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265 | |ahbo_s_ext | input |NB_AHB_SLAVE of ahb_slv_out_type |AHB Slave bus output signal | | |
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266 | |ahbi_m_ext | output |ahb_mst_In_Type|AHB Master bus input signal | | |
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267 | |ahbo_m_ext | input |NB_AHB_MASTER of ahb_mst_out_type|AHB Master bus output signal | | |
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268 | 32 | Jean-Christophe Pellion | |
269 | 21 | Jean-Christophe Pellion | }} |
270 | 22 | Jean-Christophe Pellion | |
271 | 29 | Jean-Christophe Pellion | |
272 | ---- |
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273 | |||
274 | h2. AMBA Peripherals |
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275 | |||
276 | 1 | Jean-Christophe Pellion | {{collapse(APB LFR Time Managment) |
277 | 31 | Jean-Christophe Pellion | |
278 | LFR Time management is a real time clock. The time is give by the coarse_time and fine_time value. The Time managment is like a big counter of 48b (coarse_time + fine_time). This big counter count each nb_wait_period of period clk49_152MHz. |
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279 | The bit 0 of coarse_time is the second. |
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280 | The Time mangment can be updated by register with the value into COARSE_TIME_LOAD. When a space_wire_tick or a CTRL.force_tick is asserted, the value into COARSE_TIME_LOAD is loaded in COARSE_TIME and the FINE_TIME is reset to 0. |
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281 | |||
282 | 30 | Jean-Christophe Pellion | |_.VENDOR_ID |TBD | |
283 | |_.DEVICE_ID |TBD | |
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284 | 1 | Jean-Christophe Pellion | |\2.| |
285 | |_.APB_ADDRESS |_.Register Name |_.Access |_.Description |\2.*Field* |_.Reset Value | |
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286 | |/2.0x00 |/2. CTRL |/2.RW |/2.Control register |0 | force_tick |/2.0x0 | |
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287 | |31-1 | Unused | |
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288 | 31 | Jean-Christophe Pellion | |0x04 | COARSE_TIME_LOAD |RW |CoarseTime to load after the next "tick" |31-0 | Coarse_time |0x800000000 | |
289 | |/2.0x08 |/2. COARSE_TIME |/2.R |Current CoarseTime |30-0 | Coarse_time |/2. | |
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290 | |Indicates if the current coarse_time is not "in phase" with the SPW|31 | Not_SPW | |
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291 | |/2.0x0C |/2. FINE_TIME |/2.R |/2.Current FineTime |15-0 | FineTime |/2. | |
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292 | 30 | Jean-Christophe Pellion | |31-16| Unused | |
293 | 31 | Jean-Christophe Pellion | |
294 | 30 | Jean-Christophe Pellion | <pre><code class="vhdl"> |
295 | COMPONENT apb_lfr_time_management_LPP_JCP IS |
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296 | GENERIC( |
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297 | pindex : INTEGER := 0; |
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298 | paddr : INTEGER := 0; |
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299 | pmask : INTEGER := 16#fff#; |
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300 | pirq : INTEGER := 0; |
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301 | nb_wait_period : INTEGER := 375 |
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302 | ); |
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303 | PORT ( |
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304 | clk25MHz : IN STD_LOGIC; |
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305 | clk49_152MHz : IN STD_LOGIC; |
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306 | resetn : IN STD_LOGIC; |
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307 | grspw_tick : IN STD_LOGIC; |
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308 | apbi : IN apb_slv_in_type; |
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309 | apbo : OUT apb_slv_out_type; |
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310 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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311 | fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) |
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312 | ); |
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313 | END COMPONENT; |
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314 | </code></pre> |
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315 | 34 | Jean-Christophe Pellion | |
316 | 29 | Jean-Christophe Pellion | }} |
317 | |||
318 | 22 | Jean-Christophe Pellion | ---- |