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Jean-Christophe Pellion, 28/02/2014 01:05 PM

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{{>toc}}
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h1. IP Documentation
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----
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h2. General Purpose
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h3. Edge Detection
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{{collapse(Edge_Detection)
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EdgeDetection permit to detect the edge of the sin signal.
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p=. !{width: 20%}edge_detection.png! 
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<pre><code class="vhdl">
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  COMPONENT lpp_edge_detection
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    PORT (
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      clk  : IN  STD_LOGIC;
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      rstn : IN  STD_LOGIC;
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      sin  : IN  STD_LOGIC;
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      sout : OUT STD_LOGIC);
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  END COMPONENT;
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</code></pre>
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|_.Signal      |_.Direction    |_.Size  |_.Function              |_. Active   |
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|clk           |input          |1       |clock domain 1          |rising edge |
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|rstn          |input          |1       |reset                   |low         |
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|sin           |input          |1       |signal in               |            |
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|sout          |ouput          |1       |signal out              |            |
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}}
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{{collapse(Edge_to_level)
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EdgeToLevel permit to transform the positive edge information into a level information.
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p=. !{width: 20%}edge_to_level.png! 
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<pre><code class="vhdl">
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  COMPONENT lpp_edge_to_level
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    PORT (
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      clk  : IN  STD_LOGIC;
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      rstn : IN  STD_LOGIC;
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      sin  : IN  STD_LOGIC;
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      sout : OUT STD_LOGIC);
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  END COMPONENT;
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</code></pre>
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|_.Signal      |_.Direction    |_.Size  |_.Function              |_. Active   |
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|clk           |input          |1       |clock domain 1          |rising edge |
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|rstn          |input          |1       |reset                   |low         |
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|sin           |input          |1       |signal in               |            |
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|sout          |ouput          |1       |signal out              |            |
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}}
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h3. Synchronizer
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{{collapse(SYNC_FF)
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Sync_FF permit to synchronize a signal A in the clock domain clk. Normally, A signal should be the output of a FF cloked in an other domain. You shouldtn't have "logic" between the 2 domain.
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You can configure the number FF use to synchronize (NB_FF_OF_SYNC). This number is depending of the MTBF(Mean Time Between Failure).
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p=. !{width: 15%}SYNC_FF.png!
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<pre><code class="vhdl">
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  COMPONENT SYNC_FF_LPP_JCP
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    GENERIC (
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      NB_FF_OF_SYNC : INTEGER);
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    PORT (
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      clk    : IN  STD_LOGIC;
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      rstn   : IN  STD_LOGIC;
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      A      : IN  STD_LOGIC;
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      A_sync : OUT STD_LOGIC);
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  END COMPONENT;
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</code></pre>
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|_.Parameter   |_.Type         |_.Size  |_.Description         |_.Default   |
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|NB_FF_OF_SYNC |Integer        |        |Number of FF          |2            |
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|\5.|
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|_.Signal      |_.Direction    |_.Size  |_.Function            |_. Active   |
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|clk           |input          |1       |clock                 |rising edge |
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|rstn          |input          |1       |reset                 |low         |
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|sin           |input          |1       |signal in             |            |
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|sout          |ouput          |1       |signal synchronized   |            |
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}}
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{{collapse(SYNC_VALID_BIT)
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SYNC_VALID_BIT permit to synchronize a signal of validity from clock domain clk_in to clock domain clk_out. A validity bit is a signal set "high" only one cycle and zero others. To Synchronize this type of signal, a first stage detect the positive edge, a second synchronizes this signal, and a last transform the edge information to a validity bit.
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You can configure the FF number of the second stage (NB_FF_OF_SYNC).
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p=. !{width: 20%}SYNC_VALID_BIT.png! 
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<pre><code class="vhdl">
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  COMPONENT SYNC_VALID_BIT_LPP_JCP
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    GENERIC (
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      NB_FF_OF_SYNC : INTEGER);
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    PORT (
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      clk_in  : IN  STD_LOGIC;
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      clk_out : IN  STD_LOGIC;
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      rstn    : IN  STD_LOGIC;
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      sin     : IN  STD_LOGIC;
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      sout    : OUT STD_LOGIC);
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  END COMPONENT;
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</code></pre>
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|_.Parameter   |_.Type         |_.Size  |_.Description         |_.Default   |
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|NB_FF_OF_SYNC |Integer        |        |Number of FF          |2            |
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|\5.|
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|_.Signal      |_.Direction    |_.Size  |_.Function                   |_. Active   |
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|clk_in        |input          |1       |clock domain 1               |rising edge |
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|clk_out       |input          |1       |clock domain 1               |rising edge |
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|rstn          |input          |1       |reset                        |low         |
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|sin           |input          |1       |valid bit clocked in domain 1|            |
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|sout          |output          |1      |valid bit clocked in domain 2|            |
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}}
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----
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h2. SoC (System On Chip)
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{{collapse(Leon3_Soc)
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Leon3_SoC is an IP which integrate all the basic IP for using a Leon3 System. This System is configurable :
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* activate the DSU, AHB uart, APB UART, IRQ manager and timer manager
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* activate the FPU and select the type of IP using for (netlist or rtl)
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You can connect easily external AMBA IP. For example, if you have only one Leon3 and you want to add an AHB Master My_AHB_MST. You set NB_AHB_MASTER to 1 and connect My_AHB_MST_ahbmi signal to the input ahbi_m_ext and My_AHB_MST_ahbmo to ahbo_m_ext(1).
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|_.Number            |_.NAME     |_.Enable Parameter |_.Address  |_.IRQ|
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|\5=.AHB Master |
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| 0 to NCPU-1        |leon3s     |                   |||
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| NCPU+NB_AHBMASTER  |ahbuart    |ENABLE_AHB_UART    |||
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|\5.|
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|\5=.AHB Slave |
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| 0                  |mctrl      |                   |0x00000000 |     |
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| 1                  |apbctrl    |                   |0x80000000 |     |
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| 2                  |dsu3       |ENABLE_DSU         |0x90000000 |0    |
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|\5.|
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|\5=.APB Slave |
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| 0                  |mctrl      |                   |0x80000000 |     |
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| 1                  |apbuart    |ENABLE_APB_UART    |0x80000100 |2    |
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| 2                  |irqmp      |ENABLE_IRQMP       |0x80000200 |     |
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| 3                  |gptimer    |ENABLE_GPT         |0x80000300 |8    |
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| 4                  |ahbuart    |ENABLE_APB_UART    |0x80000400 |     |
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p=. !{width: 30%}leon3_SoC.png! 
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<pre><code class="vhdl">
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  COMPONENT leon3_soc_LPP_JCP
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    GENERIC (
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      fabtech         : INTEGER;
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      memtech         : INTEGER;
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      padtech         : INTEGER;
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      clktech         : INTEGER;
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      disas           : INTEGER;
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      dbguart         : INTEGER;
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      pclow           : INTEGER;
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      clk_freq        : INTEGER;
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      NB_CPU          : INTEGER;
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      ENABLE_FPU      : INTEGER;
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      FPU_NETLIST     : INTEGER;
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      ENABLE_DSU      : INTEGER;
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      ENABLE_AHB_UART : INTEGER;
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      ENABLE_APB_UART : INTEGER;
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      ENABLE_IRQMP    : INTEGER;
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      ENABLE_GPT      : INTEGER;
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      NB_AHB_MASTER   : INTEGER;
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      NB_AHB_SLAVE    : INTEGER;
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      NB_APB_SLAVE    : INTEGER);
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    PORT (
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      clk        : IN    STD_ULOGIC;
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      rstn       : IN    STD_ULOGIC;
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      errorn     : OUT   STD_ULOGIC;
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      ahbrxd     : IN    STD_ULOGIC;
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      ahbtxd     : OUT   STD_ULOGIC;
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      urxd1      : IN    STD_ULOGIC;
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      utxd1      : OUT   STD_ULOGIC;
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      address    : OUT   STD_LOGIC_VECTOR(19 DOWNTO 0);
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      data       : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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      nSRAM_BE0  : OUT   STD_LOGIC;
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      nSRAM_BE1  : OUT   STD_LOGIC;
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      nSRAM_BE2  : OUT   STD_LOGIC;
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      nSRAM_BE3  : OUT   STD_LOGIC;
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      nSRAM_WE   : OUT   STD_LOGIC;
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      nSRAM_CE   : OUT   STD_LOGIC;
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      nSRAM_OE   : OUT   STD_LOGIC;
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      apbi_ext   : OUT   apb_slv_in_type;
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      apbo_ext   : IN    soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
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      ahbi_s_ext : OUT   ahb_slv_in_type;
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      ahbo_s_ext : IN    soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
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      ahbi_m_ext : OUT   AHB_Mst_In_Type;
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      ahbo_m_ext : IN    soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
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  END COMPONENT;
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</code></pre>
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|_.Parameter     |_.Type       |_.Size  |_.Description         |_.Default   |
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|fabtech         | INTEGER     |        |Target technologie                      |apa3e       |
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|memtech         | INTEGER     |        |Memory Target technologie                      |apa3e       |
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|padtech         | INTEGER     |        |Pad Target technologie                      |inferred    |
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|clktech         | INTEGER     |        |Clock target technologie                      |inferred    |
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|disas           | INTEGER     |        |Activate the disassembler  |0           |
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|dbguart         | INTEGER     |        |Activate debug uart                      |0           |
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|pclow           | INTEGER     |        |                      |2           |
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|clk_freq        | INTEGER     |        |Clock input frequency (in kHz)                      |25000       |
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|NB_CPU          | INTEGER     |        |Number of Leon3                      |1           |
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|ENABLE_FPU      | INTEGER     |        |Enable the FPU                      |1           |
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|FPU_NETLIST     | INTEGER     |        |Select the FPU Used (1=> NetList, 0=> RTL)   |1           |
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|ENABLE_DSU      | INTEGER     |        |Enable the Debug System Unit                      |1           |
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|ENABLE_AHB_UART | INTEGER     |        |Enable AHB UART                      |1           |
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|ENABLE_APB_UART | INTEGER     |        |Enable APB UART                      |1           |
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|ENABLE_IRQMP    | INTEGER     |        |Enable irq manager                      |1           |
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|ENABLE_GPT      | INTEGER     |        |Enable the timer                      |1           |
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|NB_AHB_MASTER   | INTEGER     |        |Number of AHB Master outside the SoC                      |0           |
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|NB_AHB_SLAVE    | INTEGER     |        |Number of AHB Slave outside the SoC                      |0           |
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|NB_APB_SLAVE    | INTEGER     |        |Number of APB Slave outside the SoC                      |0           |
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|\5.|
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|_.Signal   |_.Direction    |_.Size or Type |_.Function                   |_. Active   |
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|clk        | input         |1              |clock                        |rising edge |
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|rstn       | input         |1              |reset                        |low         |
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|errorn     | output        |1              |leon 3 error signal          |            |
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|ahbrxd     | input         |1              |AHB uart Rx Signal           |            |
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|ahbtxd     | output        |1              |AHB uart Tx Signal           |            |
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|urxd1      | input         |1              |APB uart Rx Signal           |            |
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|utxd1      | output        |1              |APB uart Tx Signal           |            |
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|address    | output        |20             |SRam  Address                |            |
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|data       | inout         |32             |SRam Data                    |            |
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|nSRAM_BE0  | output        |1              |SRam bankEnable  0           |            |
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|nSRAM_BE1  | output        |1              |SRam bankEnable  1           |            |
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|nSRAM_BE2  | output        |1              |SRam bankEnable  2           |            |
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|nSRAM_BE3  | output        |1              |SRam bankEnable  3           |            |
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|nSRAM_WE   | output        |1              |SRam WriteEnable             |            |
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|nSRAM_CE   | output        |1              |SRam ChipEnable                             |            |
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|nSRAM_OE   | output        |1              |SRam OutputEnable                             |            |
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|apbi_ext   | output        |apb_slv_in_type|APB Slave bus input signal                             |            |
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|apbo_ext   | input         |NB_APB_SLAVE of apb_slv_out_type|APB Slave bus output signal                            |            |
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|ahbi_s_ext | output        |ahb_slv_in_type|AHB Slave bus input signal                              |            |
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|ahbo_s_ext | input         |NB_AHB_SLAVE of ahb_slv_out_type |AHB Slave bus output signal                            |            |
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|ahbi_m_ext | output        |ahb_mst_In_Type|AHB Master bus input signal                             |            |
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|ahbo_m_ext | input         |NB_AHB_MASTER of ahb_mst_out_type|AHB Master bus output signal                              |            |
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}}
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----