IP documentation

EdgeDetection permit to detect the edge of the sin signal.

p=. !{width: 20%}edge_detection.png!

COMPONENT lpp_edge_detection
PORT (
clk : IN STD_LOGIC;
rstn : IN STD_LOGIC;
sin : IN STD_LOGIC;
sout : OUT STD_LOGIC);
END COMPONENT;

EdgeToLevel permit to transform the positive edge information into a level information.

p=. !{width: 20%}edge_to_level.png!

COMPONENT lpp_edge_to_level
PORT (
clk : IN STD_LOGIC;
rstn : IN STD_LOGIC;
sin : IN STD_LOGIC;
sout : OUT STD_LOGIC);
END COMPONENT;

Sync_FF permit to synchronize a signal A in the clock domain clk. Normally, A signal should be the output of a FF cloked in an other domain. You shouldtn't have "logic" between the 2 domain.
You can configure the number FF use to synchronize (NB_FF_OF_SYNC). This number is depending of the MTBF(Mean Time Between Failure).

p=. !{width: 15%}SYNC_FF.png!

COMPONENT SYNC_FF_LPP_JCP
GENERIC (
NB_FF_OF_SYNC : INTEGER);
PORT (
clk : IN STD_LOGIC;
rstn : IN STD_LOGIC;
A : IN STD_LOGIC;
A_sync : OUT STD_LOGIC);
END COMPONENT;

SYNC_VALID_BIT permit to synchronize a signal of validity from clock domain clk_in to clock domain clk_out. A validity bit is a signal set "high" only one cycle and zero others. To Synchronize this type of signal, a first stage detect the positive edge, a second synchronizes this signal, and a last transform the edge information to a validity bit.
You can configure the FF number of the second stage (NB_FF_OF_SYNC).

p=. !{width: 20%}SYNC_VALID_BIT.png!

COMPONENT SYNC_VALID_BIT_LPP_JCP
GENERIC (
NB_FF_OF_SYNC : INTEGER);
PORT (
clk_in : IN STD_LOGIC;
clk_out : IN STD_LOGIC;
rstn : IN STD_LOGIC;
sin : IN STD_LOGIC;
sout : OUT STD_LOGIC);
END COMPONENT;

Leon3_SoC is an IP which integrate all the basic IP for using a Leon3 System. This System is configurable :

activate the DSU, AHB uart, APB UART, IRQ manager and timer manager
activate the FPU and select the type of IP using for (netlist or rtl)

You can connect easily external AMBA IP. For example, if you have only one Leon3 and you want to add an AHB Master My_AHB_MST. You set NB_AHB_MASTER to 1 and connect My_AHB_MST_ahbmi signal to the input ahbi_m_ext and My_AHB_MST_ahbm0 to ahbo_m_ext(1).

COMPONENT leon3_soc_LPP_JCP
GENERIC (
fabtech : INTEGER;
memtech : INTEGER;
padtech : INTEGER;
clktech : INTEGER;
disas : INTEGER;
dbguart : INTEGER;
pclow : INTEGER;
clk_freq : INTEGER;
NB_CPU : INTEGER;
ENABLE_FPU : INTEGER;
FPU_NETLIST : INTEGER;
ENABLE_DSU : INTEGER;
ENABLE_AHB_UART : INTEGER;
ENABLE_APB_UART : INTEGER;
ENABLE_IRQMP : INTEGER;
ENABLE_GPT : INTEGER;
NB_AHB_MASTER : INTEGER;
NB_AHB_SLAVE : INTEGER;
NB_APB_SLAVE : INTEGER);
PORT (
clk : IN STD_ULOGIC;
rstn : IN STD_ULOGIC;
errorn : OUT STD_ULOGIC;
ahbrxd : IN STD_ULOGIC;
ahbtxd : OUT STD_ULOGIC;
urxd1 : IN STD_ULOGIC;
utxd1 : OUT STD_ULOGIC;
address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
nSRAM_BE0 : OUT STD_LOGIC;
nSRAM_BE1 : OUT STD_LOGIC;
nSRAM_BE2 : OUT STD_LOGIC;
nSRAM_BE3 : OUT STD_LOGIC;
nSRAM_WE : OUT STD_LOGIC;
nSRAM_CE : OUT STD_LOGIC;
nSRAM_OE : OUT STD_LOGIC;
apbi_ext : OUT apb_slv_in_type;
apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
ahbi_s_ext : OUT ahb_slv_in_type;
ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
ahbi_m_ext : OUT AHB_Mst_In_Type;
ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
END COMPONENT;