IP documentation » History » Revision 19
Revision 18 (Jean-Christophe Pellion, 27/02/2014 05:52 PM) → Revision 19/38 (Jean-Christophe Pellion, 27/02/2014 05:55 PM)
{{>toc}}
h1. IP Documentation
----
h2. General Purpose
h3. Edge Detection
{{collapse(Edge_Detection)
EdgeDetection permit to detect the edge of the sin signal.
p=. !{width: 20%}edge_detection.png!
<pre><code class="vhdl">
COMPONENT lpp_edge_detection
PORT (
clk : IN STD_LOGIC;
rstn : IN STD_LOGIC;
sin : IN STD_LOGIC;
sout : OUT STD_LOGIC);
END COMPONENT;
</code></pre>
|_.Signal |_.Direction |_.Size |_.Function |_. Active |
|clk |input |1 |clock domain 1 |rising edge |
|rstn |input |1 |reset |low |
|sin |input |1 |signal in | |
|sout |ouput |1 |signal out | |
}}
{{collapse(Edge_to_level)
EdgeToLevel ...
p=. !{width: 20%}edge_to_level.png!
<pre><code class="vhdl">
COMPONENT lpp_edge_to_level
PORT (
clk : IN STD_LOGIC;
rstn : IN STD_LOGIC;
sin : IN STD_LOGIC;
sout : OUT STD_LOGIC);
END COMPONENT;
</code></pre>
|_.Signal |_.Direction |_.Size |_.Function |_. Active |
|clk |input |1 |clock domain 1 |rising edge |
|rstn |input |1 |reset |low |
|sin |input |1 |signal in | |
|sout |ouput |1 |signal out | |
}}
h3. Synchronizer
{{collapse(SYNC_FF)
Sync_FF permit to synchronize a signal A in the clock domain clk. Normally, the A signal should must be the output of a FF cloked in an other domain. You shouldtn't have "logic" between the 2 domain.
You can configure the FF number FF use to synchronize (NB_FF_OF_SYNC). (default 2). This number is depending of the MTBF(Mean Time Between Failure).
p=. !{width: 15%}SYNC_FF.png!
<pre><code class="vhdl">
COMPONENT SYNC_FF_LPP_JCP
GENERIC (
NB_FF_OF_SYNC : INTEGER);
PORT (
clk : IN STD_LOGIC;
rstn : IN STD_LOGIC;
A : IN STD_LOGIC;
A_sync : OUT STD_LOGIC);
END COMPONENT;
</code></pre>
|_.Parameter |_.Type |_.Size |_.Description |_.Default |
|NB_FF_OF_SYNC |Integer | |Number of FF |2 |
|\5.|
|_.Signal |_.Direction |_.Size |_.Function |_. Active |
|clk |input |1 |clock |rising edge |
|rstn |input |1 |reset |low |
|sin |input |1 |signal in | |
|sout |ouput |1 |signal synchronized | |
}}
{{collapse(SYNC_VALID_BIT)
SYNC_VALID_BIT permit to synchronize a signal of validity from clock domain clk_in to clock domain clk_out. A validity bit is a signal set "high" only one cycle and zero others. To Synchronize this type of signal, a first stage detect the positive edge, a second synchronizes this signal, and a last transform the edge information to a validity bit.
You can configure the FF number of the second stage (NB_FF_OF_SYNC).
p=. !{width: 20%}SYNC_VALID_BIT.png!
<pre><code class="vhdl">
COMPONENT SYNC_VALID_BIT_LPP_JCP
GENERIC (
NB_FF_OF_SYNC : INTEGER);
PORT (
clk_in : IN STD_LOGIC;
clk_out : IN STD_LOGIC;
rstn : IN STD_LOGIC;
sin : IN STD_LOGIC;
sout : OUT STD_LOGIC);
END COMPONENT;
</code></pre>
|_.Parameter |_.Type |_.Size |_.Description |_.Default |
|NB_FF_OF_SYNC |Integer | |Number of FF |2 |
|\5.|
|_.Signal |_.Direction |_.Size |_.Function |_. Active |
|clk_in |input |1 |clock domain 1 |rising edge |
|clk_out |input |1 |clock domain 1 |rising edge |
|rstn |input |1 |reset |low |
|sin |input |1 |valid bit clocked in domain 1| |
|sout |output |1 |valid bit clocked in domain 2| |
}}