{{>toc}}

h1. IP Documentation

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h2. General Purpose

h3. Edge Detection

{{collapse(Edge_Detection)
EdgeDetection permit to detect the edge of the sin signal.

p=. !{width: 20%}edge_detection.png! 

<pre><code class="vhdl">
  COMPONENT lpp_edge_detection
    PORT (
      clk  : IN  STD_LOGIC;
      rstn : IN  STD_LOGIC;
      sin  : IN  STD_LOGIC;
      sout : OUT STD_LOGIC);
  END COMPONENT;
</code></pre>

|_.Signal      |_.Direction    |_.Size  |_.Function              |_. Active   |
|clk           |input          |1       |clock domain 1          |rising edge |
|rstn          |input          |1       |reset                   |low         |
|sin           |input          |1       |signal in               |            |
|sout          |ouput          |1       |signal out              |            |

}}
{{collapse(Edge_to_level)
EdgeToLevel ...

p=. !{width: 20%}edge_to_level.png! 

<pre><code class="vhdl">
  COMPONENT lpp_edge_detection
    PORT (
      clk  : IN  STD_LOGIC;
      rstn : IN  STD_LOGIC;
      sin  : IN  STD_LOGIC;
      sout : OUT STD_LOGIC);
  END COMPONENT;
</code></pre>

|_.Signal      |_.Direction    |_.Size  |_.Function              |_. Active   |
|clk           |input          |1       |clock domain 1          |rising edge |
|rstn          |input          |1       |reset                   |low         |
|sin           |input          |1       |signal in               |            |
|sout          |ouput          |1       |signal out              |            |

}}

h3. Synchronizer

{{collapse(SYNC_FF)
Sync_FF permit to synchronize a signal A in the clock domain clk. Normally, the A signal must be the output of a FF cloked in an other domain. You shouldtn't have "logic" between the 2 domain.
You can configure the FF number (default 2). This number is depending of the MTBF(Mean Time Between Failure).

p=. !{width: 15%}SYNC_FF.png!

<pre><code class="vhdl">
  COMPONENT SYNC_FF_LPP_JCP
    GENERIC (
      NB_FF_OF_SYNC : INTEGER);
    PORT (
      clk    : IN  STD_LOGIC;
      rstn   : IN  STD_LOGIC;
      A      : IN  STD_LOGIC;
      A_sync : OUT STD_LOGIC);
  END COMPONENT;
</code></pre>

|_.Parameter   |_.Type         |_.Size  |_.Description         |_.Default   |
|NB_FF_OF_SYNC |Integer        |        |Number of FF          |2            |
|\5.|
|_.Signal      |_.Direction    |_.Size  |_.Function            |_. Active   |
|clk           |input          |1       |clock                 |rising edge |
|rstn          |input          |1       |reset                 |low         |
|sin           |input          |1       |signal in             |            |
|sout          |ouput          |1       |signal synchronized   |            |

}}

{{collapse(SYNC_VALID_BIT)
SYNC_VALID_BIT permit to synchronize a signal sin from clock domain clk_in in clock domain clk_out. The sin signal is clocked with one FF in clk_in domain and NB_FF_OF_SYNC in clk_out domain.
You can configure the FF number (default 2). This number is depending of the MTBF(Mean Time Between Failure).

p=. !{width: 20%}SYNC_VALID_BIT.png! 

<pre><code class="vhdl">
  COMPONENT SYNC_VALID_BIT_LPP_JCP
    GENERIC (
      NB_FF_OF_SYNC : INTEGER);
    PORT (
      clk_in  : IN  STD_LOGIC;
      clk_out : IN  STD_LOGIC;
      rstn    : IN  STD_LOGIC;
      sin     : IN  STD_LOGIC;
      sout    : OUT STD_LOGIC);
  END COMPONENT;
</code></pre>

|_.Parameter   |_.Type         |_.Size  |_.Description         |_.Default   |
|NB_FF_OF_SYNC |Integer        |        |Number of FF          |2            |
|\5.|
|_.Signal      |_.Direction    |_.Size  |_.Function              |_. Active   |
|clk_in        |input          |1       |clock domain 1          |rising edge |
|clk_out       |input          |1       |clock domain 1          |rising edge |
|rstn          |input          |1       |reset                   |low         |
|sin           |input          |1       |data clocked in domain 1|            |
|sout          |output          |1       |data clocked in domain 2|            |

}}