IP documentation » History » Version 15
Jean-Christophe Pellion, 27/02/2014 05:36 PM
1 | 10 | Jean-Christophe Pellion | {{>toc}} |
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2 | 1 | Jean-Christophe Pellion | |
3 | 11 | Jean-Christophe Pellion | h1. IP Documentation |
4 | 1 | Jean-Christophe Pellion | |
5 | 15 | Jean-Christophe Pellion | ---- |
6 | |||
7 | 11 | Jean-Christophe Pellion | h2. General Purpose |
8 | 1 | Jean-Christophe Pellion | |
9 | 15 | Jean-Christophe Pellion | h3. Edge Detection |
10 | 1 | Jean-Christophe Pellion | |
11 | 15 | Jean-Christophe Pellion | {{collapse(Edge_Detection) |
12 | EdgeDetection permit to detect the edge of the sin signal. |
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13 | |||
14 | p=. !{width: 20%}edge_detection.png! |
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15 | |||
16 | <pre><code class="vhdl"> |
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17 | COMPONENT lpp_edge_detection |
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18 | PORT ( |
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19 | clk : IN STD_LOGIC; |
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20 | rstn : IN STD_LOGIC; |
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21 | sin : IN STD_LOGIC; |
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22 | sout : OUT STD_LOGIC); |
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23 | END COMPONENT; |
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24 | </code></pre> |
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25 | |||
26 | |_.Signal |_.Direction |_.Size |_.Function |_. Active | |
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27 | |clk |input |1 |clock domain 1 |rising edge | |
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28 | |rstn |input |1 |reset |low | |
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29 | |sin |input |1 |signal in | | |
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30 | |sout |ouput |1 |signal out | | |
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31 | |||
32 | }} |
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33 | {{collapse(Edge_to_level) |
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34 | EdgeToLevel ... |
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35 | |||
36 | p=. !{width: 20%}edge_detection.png! |
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37 | |||
38 | <pre><code class="vhdl"> |
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39 | COMPONENT lpp_edge_detection |
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40 | PORT ( |
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41 | clk : IN STD_LOGIC; |
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42 | rstn : IN STD_LOGIC; |
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43 | sin : IN STD_LOGIC; |
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44 | sout : OUT STD_LOGIC); |
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45 | END COMPONENT; |
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46 | </code></pre> |
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47 | |||
48 | |_.Signal |_.Direction |_.Size |_.Function |_. Active | |
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49 | |clk |input |1 |clock domain 1 |rising edge | |
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50 | |rstn |input |1 |reset |low | |
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51 | |sin |input |1 |signal in | | |
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52 | |sout |ouput |1 |signal out | | |
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53 | |||
54 | }} |
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55 | |||
56 | 13 | Jean-Christophe Pellion | h3. Synchronizer |
57 | 8 | Jean-Christophe Pellion | |
58 | {{collapse(SYNC_FF) |
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59 | 1 | Jean-Christophe Pellion | Sync_FF permit to synchronize a signal A in the clock domain clk. Normally, the A signal must be the output of a FF cloked in an other domain. You shouldtn't have "logic" between the 2 domain. |
60 | 14 | Jean-Christophe Pellion | You can configure the FF number (default 2). This number is depending of the MTBF(Mean Time Between Failure). |
61 | 13 | Jean-Christophe Pellion | |
62 | p=. !{width: 15%}SYNC_FF.png! |
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63 | 8 | Jean-Christophe Pellion | |
64 | <pre><code class="vhdl"> |
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65 | COMPONENT SYNC_FF_LPP_JCP |
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66 | GENERIC ( |
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67 | NB_FF_OF_SYNC : INTEGER); |
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68 | PORT ( |
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69 | clk : IN STD_LOGIC; |
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70 | rstn : IN STD_LOGIC; |
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71 | A : IN STD_LOGIC; |
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72 | A_sync : OUT STD_LOGIC); |
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73 | END COMPONENT; |
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74 | </code></pre> |
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75 | |||
76 | |_.Parameter |_.Type |_.Size |_.Description |_.Default | |
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77 | 7 | Jean-Christophe Pellion | |NB_FF_OF_SYNC |Integer | |Number of FF |2 | |
78 | 1 | Jean-Christophe Pellion | |\5.| |
79 | |_.Signal |_.Direction |_.Size |_.Function |_. Active | |
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80 | |clk |input |1 |clock |rising edge | |
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81 | |rstn |input |1 |reset |low | |
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82 | 15 | Jean-Christophe Pellion | |sin |input |1 |signal in | | |
83 | |sout |ouput |1 |signal synchronized | | |
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84 | 13 | Jean-Christophe Pellion | |
85 | }} |
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86 | |||
87 | 14 | Jean-Christophe Pellion | {{collapse(SYNC_VALID_BIT) |
88 | 13 | Jean-Christophe Pellion | SYNC_VALID_BIT permit to synchronize a signal sin from clock domain clk_in in clock domain clk_out. The sin signal is clocked with one FF in clk_in domain and NB_FF_OF_SYNC in clk_out domain. |
89 | You can configure the FF number (default 2). This number is depending of the MTBF(Mean Time Between Failure). |
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90 | 14 | Jean-Christophe Pellion | |
91 | 13 | Jean-Christophe Pellion | p=. !{width: 20%}SYNC_VALID_BIT.png! |
92 | |||
93 | <pre><code class="vhdl"> |
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94 | COMPONENT SYNC_VALID_BIT_LPP_JCP |
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95 | GENERIC ( |
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96 | NB_FF_OF_SYNC : INTEGER); |
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97 | PORT ( |
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98 | clk_in : IN STD_LOGIC; |
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99 | clk_out : IN STD_LOGIC; |
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100 | rstn : IN STD_LOGIC; |
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101 | sin : IN STD_LOGIC; |
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102 | sout : OUT STD_LOGIC); |
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103 | END COMPONENT; |
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104 | </code></pre> |
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105 | |||
106 | |_.Parameter |_.Type |_.Size |_.Description |_.Default | |
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107 | |NB_FF_OF_SYNC |Integer | |Number of FF |2 | |
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108 | |\5.| |
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109 | |_.Signal |_.Direction |_.Size |_.Function |_. Active | |
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110 | 1 | Jean-Christophe Pellion | |clk_in |input |1 |clock domain 1 |rising edge | |
111 | 13 | Jean-Christophe Pellion | |clk_out |input |1 |clock domain 1 |rising edge | |
112 | |rstn |input |1 |reset |low | |
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113 | |sin |input |1 |data clocked in domain 1| | |
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114 | 15 | Jean-Christophe Pellion | |sout |output |1 |data clocked in domain 2| | |
115 | 2 | Jean-Christophe Pellion | |
116 | }} |