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IP documentation » History » Version 14

Jean-Christophe Pellion, 27/02/2014 04:46 PM

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{{>toc}}
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h1. IP Documentation
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h2. General Purpose
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h3. Synchronizer
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{{collapse(SYNC_FF)
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Sync_FF permit to synchronize a signal A in the clock domain clk. Normally, the A signal must be the output of a FF cloked in an other domain. You shouldtn't have "logic" between the 2 domain.
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You can configure the FF number (default 2). This number is depending of the MTBF(Mean Time Between Failure).
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p=. !{width: 15%}SYNC_FF.png!
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<pre><code class="vhdl">
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  COMPONENT SYNC_FF_LPP_JCP
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    GENERIC (
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      NB_FF_OF_SYNC : INTEGER);
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    PORT (
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      clk    : IN  STD_LOGIC;
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      rstn   : IN  STD_LOGIC;
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      A      : IN  STD_LOGIC;
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      A_sync : OUT STD_LOGIC);
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  END COMPONENT;
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</code></pre>
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|_.Parameter   |_.Type         |_.Size  |_.Description         |_.Default   |
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|NB_FF_OF_SYNC |Integer        |        |Number of FF          |2            |
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|\5.|
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|_.Signal      |_.Direction    |_.Size  |_.Function            |_. Active   |
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|clk           |input          |1       |clock                 |rising edge |
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|rstn          |input          |1       |reset                 |low         |
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|A             |input          |1       |data in               |            |
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|A_sync        |ouput          |1       |data out synchronized |            |
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}}
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{{collapse(SYNC_VALID_BIT)
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SYNC_VALID_BIT permit to synchronize a signal sin from clock domain clk_in in clock domain clk_out. The sin signal is clocked with one FF in clk_in domain and NB_FF_OF_SYNC in clk_out domain.
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You can configure the FF number (default 2). This number is depending of the MTBF(Mean Time Between Failure).
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p=. !{width: 20%}SYNC_VALID_BIT.png! 
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<pre><code class="vhdl">
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  COMPONENT SYNC_VALID_BIT_LPP_JCP
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    GENERIC (
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      NB_FF_OF_SYNC : INTEGER);
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    PORT (
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      clk_in  : IN  STD_LOGIC;
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      clk_out : IN  STD_LOGIC;
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      rstn    : IN  STD_LOGIC;
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      sin     : IN  STD_LOGIC;
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      sout    : OUT STD_LOGIC);
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  END COMPONENT;
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</code></pre>
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|_.Parameter   |_.Type         |_.Size  |_.Description         |_.Default   |
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|NB_FF_OF_SYNC |Integer        |        |Number of FF          |2            |
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|\5.|
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|_.Signal      |_.Direction    |_.Size  |_.Function              |_. Active   |
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|clk_in        |input          |1       |clock domain 1          |rising edge |
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|clk_out       |input          |1       |clock domain 1          |rising edge |
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|rstn          |input          |1       |reset                   |low         |
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|sin           |input          |1       |data clocked in domain 1|            |
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|A_sync        |ouput          |1       |data clocked in domain 2|            |
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}}