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# Tracker Status Priority Subject Assignee Updated
555 Task Closed Normal Errata RPW-MEB-LFR-SPC-00061-1-8_FPGA_Architecture_Design Jean-Christophe Pellion 26/10/2015 04:20 PM Actions
496 Bug Closed Urgent Bistream 1.1.89 tests ctc200_2015_09_10 paul leroy 12/10/2015 07:52 AM Actions
476 Bug Closed Urgent Bistream 1.1.88 tests ctc200_2015_07_23 thomas chust 22/06/2018 05:08 PM Actions
472 Bug Closed Normal Bistream 1.1.85 pb temps ASM et CWF_LONG thomas chust 07/10/2015 06:08 PM Actions
403 Task Rejected Low Evaluate some opensource VHDL IPs Alexis Jeandet 28/07/2015 05:35 PM Actions
361 Task Closed Normal Design DiscoSpace paul leroy 09/06/2015 10:48 AM Actions
313 Bug Closed Normal Indices de fréquences des ASM décalés de 1 à gauche paul leroy 07/04/2015 04:05 PM Actions
312 Feature Closed Normal signaux tests pour CoreFFT (Actel) (série 1) thomas chust 28/01/2015 05:19 PM Actions
307 Bug Closed Normal numéro de version du VHDL non accessible après un reset HW paul leroy 05/02/2015 08:32 AM Actions
266 Bug Closed Normal tests préliminaires sur design 0.1.32 paul leroy 10/02/2015 09:02 AM Actions
258 Support Closed Normal Numéro de version du code VHDL Jean-Christophe Pellion 10/02/2015 04:27 PM Actions
239 Task Closed Normal Parametre R2 du Waveform Picker - Doc and Verif paul leroy 10/02/2015 09:05 AM Actions
234 Bug Closed Normal Problème sur la forme d'onde ("écrêtage" vers 1.5 V d'amplitudes) Jean-Christophe Pellion 02/10/2014 09:26 AM Actions
233 Task Closed Normal retrofit FPGA sur EM+ Alexis Jeandet 28/07/2015 05:38 PM Actions
230 Task Closed Normal Rédaction de la demande de modification pour STEEL Vincent Leray 08/04/2015 07:47 AM Actions
227 Task Closed Normal Calibration Jean-Christophe Pellion 10/02/2015 04:22 PM Actions
125 Bug Closed High LFR ADC data justification paul leroy 10/02/2015 09:03 AM Actions
33 Feature Closed Normal sous-échantillonnage des signaux électriques DC (s1, s2 et s3) Jean-Christophe Pellion 03/09/2014 09:42 AM Actions
32 Feature Closed Normal implémenter un masque sur les spectres paul leroy 10/02/2015 03:23 PM Actions
31 Feature Closed Normal filtrage + sous échantillonnage 8 voies Jean-Christophe Pellion 03/09/2014 09:42 AM Actions
30 Feature Closed Normal Document types creation Alexis Jeandet 13/12/2013 04:22 PM Actions
19 Task Closed Normal Sélection du sous-traitant pour les réalisation QM/FM/SM et boitiers paul leroy 10/02/2015 03:20 PM Actions
17 Task Closed Normal Finalisation des développements du module Spectral Matrices Martin Morlot 27/08/2014 10:27 AM Actions
14 Task Closed High Fichier de configuration FPGA Jean-Christophe Pellion 13/03/2014 07:17 AM Actions
13 Task Closed Normal Mise à jour de la documentation VHDL Jean-Christophe Pellion 13/03/2014 07:17 AM Actions
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