Leon3FT fault tolerance » History » Revision 6
Revision 5 (paul leroy, 25/01/2016 01:51 PM) → Revision 6/18 (paul leroy, 25/01/2016 01:53 PM)
h1. Leon3/FT fault tolerance The explanations hereafter are extracted from the Gaisler IP cores user's manual (grip.pdf). There are two aspects in the fault tolerance: register file protection and cache protection. Each aspect is managed using a specific register: * Cache protection is managed with the CCR (Cache Control Register) located in ASI 2, offet 0x00 * Register file protection is managed with the ASR16, Register protection control register h2. Cache Control Register (ASI 2, offset 0x00) Cache Control Register Leon3 / Leon3FT 31..30 29 28 27..24 23 22 21 20..19 18 17 16 RFT PS TB DS FD FI FT ST IB 15 14 13..12 11..10 9..8 7..6 5 4 3..2 1..0 IP DP ITE IDE DTE DDE DF IF DCS ICS h2. Register protection control register (ASR16) ASR register 16 (%asr16) is used to control the IU/FPU register file SEU protection. It is possible to disable the SEU protection by setting the IDI/FDI bits, and to inject errors using the ITE/FTE bits. Corrected errors in the register file are counted, and available in ICNT and FCNT fields. The counters saturate at their maximum value (7), and should be reset by software after read-out. *ASI = Address Space Identifier *ASR = Ancillary State Register