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1 : /*------------------------------------------------------------------------------ 2 : -- Solar Orbiter's Low Frequency Receiver Flight Software (LFR FSW), 3 : -- This file is a part of the LFR FSW 4 : -- Copyright (C) 2021, Plasma Physics Laboratory - CNRS 5 : -- 6 : -- This program is free software; you can redistribute it and/or modify 7 : -- it under the terms of the GNU General Public License as published by 8 : -- the Free Software Foundation; either version 2 of the License, or 9 : -- (at your option) any later version. 10 : -- 11 : -- This program is distributed in the hope that it will be useful, 12 : -- but WITHOUT ANY WARRANTY; without even the implied warranty of 13 : -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 : -- GNU General Public License for more details. 15 : -- 16 : -- You should have received a copy of the GNU General Public License 17 : -- along with this program; if not, write to the Free Software 18 : -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 : -------------------------------------------------------------------------------*/ 20 : /*-- Author : Alexis Jeandet 21 : -- Contact : Alexis Jeandet 22 : -- Mail : alexis.jeandet@lpp.polytechnique.fr 23 : ----------------------------------------------------------------------------*/ 24 : #include "hw/timer.h" 25 : #include "fsw_globals.h" 26 : #include "fsw_debug.h" 27 : #include "hw/lfr_regs.h" 28 : 29 18 : void timer_configure(unsigned char timer, unsigned int clock_divider, unsigned char interrupt_level, 30 : rtems_isr (*timer_isr)()) 31 : { 32 : /** This function configures a GPTIMER timer instantiated in the VHDL design. 33 : * 34 : * @param gptimer_regs points to the APB registers of the GPTIMER IP core. 35 : * @param timer is the number of the timer in the IP core (several timers can be instantiated). 36 : * @param clock_divider is the divider of the 1 MHz clock that will be configured. 37 : * @param interrupt_level is the interrupt level that the timer drives. 38 : * @param timer_isr is the interrupt subroutine that will be attached to the IRQ driven by the 39 : * timer. 40 : * 41 : * Interrupt levels are described in the SPARC documentation sparcv8.pdf p.76 42 : * 43 : */ 44 : 45 : rtems_status_code status; 46 : rtems_isr_entry old_isr_handler; 47 : 48 18 : old_isr_handler = NULL; 49 : 50 18 : gptimer0->timer[timer].ctrl = INIT_CHAR; // reset the control register 51 : 52 18 : status = rtems_interrupt_catch( 53 : timer_isr, interrupt_level, &old_isr_handler); // see sparcv8.pdf p.76 for interrupt levels 54 18 : if (status != RTEMS_SUCCESSFUL) 55 : { 56 : LFR_PRINTF("in configure_timer *** ERR rtems_interrupt_catch\n"); 57 : } 58 : 59 18 : timer_set_clock_divider(timer, clock_divider); 60 18 : } 61 : 62 : 63 0 : void timer_stop(unsigned char timer) 64 : { 65 : /** This function stops a GPTIMER timer. 66 : * 67 : * @param timer is the number of the timer in the IP core (several timers can be instantiated). 68 : * 69 : */ 70 : 71 0 : gptimer0->timer[timer].ctrl = gptimer0->timer[timer].ctrl & GPTIMER_EN_MASK; 72 0 : gptimer0->timer[timer].ctrl = gptimer0->timer[timer].ctrl & GPTIMER_IE_MASK; 73 0 : gptimer0->timer[timer].ctrl = gptimer0->timer[timer].ctrl | GPTIMER_CLEAR_IRQ; 74 0 : } 75 : 76 0 : void timer_set_clock_divider(unsigned char timer, unsigned int clock_divider) 77 : { 78 : /** This function sets the clock divider of a GPTIMER timer. 79 : * 80 : * @param timer is the number of the timer in the IP core (several timers can be instantiated). 81 : * @param clock_divider is the divider of the 1 MHz clock that will be configured. 82 : * 83 : */ 84 : 85 18 : gptimer0->timer[timer].reload = clock_divider; // base clock frequency is 1 MHz 86 0 : }