LCOV - code coverage report
Current view: top level - header - GscMemoryLPP.hpp (source / functions) Hit Total Coverage
Test: trace.info Lines: 19 36 52.8 %
Date: 2023-02-20 11:47:14 Functions: 1 3 33.3 %

          Line data    Source code
       1             : #ifndef GSCMEMORY_HPP_
       2             : #define GSCMEMORY_HPP_
       3             : 
       4             : #include "lfr_common_headers/fsw_params.h"
       5             : #include "fsw_debug.h"
       6             : 
       7             : #ifndef LEON3
       8             :     #define LEON3
       9             : #endif
      10             : 
      11             : #define REGS_ADDR_PLUGANDPLAY 0xFFFFF000
      12             : #define ASR16_REG_ADDRESS                                                                          \
      13             :     0x90400040 // Ancillary State Register 16 = Register protection control register (FT only)
      14             : 
      15             : #define DEVICEID_LEON3   0x003
      16             : #define DEVICEID_LEON3FT 0x053
      17             : #define VENDORID_GAISLER 0x01
      18             : 
      19             : // CCR
      20             : #define POS_FT 19
      21             : //
      22             : #define POS_ITE           12
      23             : #define COUNTER_FIELD_ITE 0x00003000 // 0000 0000 0000 0000 0011 0000 0000 0000
      24             : #define COUNTER_MASK_ITE  0xffffcfff // 1111 1111 1111 1111 1100 1111 1111 1111
      25             : #define POS_IDE           10
      26             : #define COUNTER_FIELD_IDE 0x00000c00 // 0000 0000 0000 0000 0000 1100 0000 0000
      27             : #define COUNTER_MASK_IDE  0xfffff3ff // 1111 1111 1111 1111 1111 0011 1111 1111
      28             : //
      29             : #define POS_DTE           8
      30             : #define COUNTER_FIELD_DTE 0x00000300 // 0000 0000 0000 0000 0000 0011 0000 0000
      31             : #define COUNTER_MASK_DTE  0xfffffcff // 1111 1111 1111 1111 1111 1100 1111 1111
      32             : #define POS_DDE           6
      33             : #define COUNTER_FIELD_DDE 0x000000c0 // 0000 0000 0000 0000 0000 0000 1100 0000
      34             : #define COUNTER_MASK_DDE  0xffffff3f // 1111 1111 1111 1111 1111 1111 0011 1111
      35             : 
      36             : // ASR16
      37             : #define POS_FPFTID 30
      38             : #define POS_FPRF   27
      39             : #define POS_FDI    16 // FP RF protection enable/disable
      40             : #define POS_IUFTID 14
      41             : #define POS_IURF   11
      42             : #define POS_IDI    0 // IU RF protection enable/disable
      43             : 
      44             : #define COUNTER_FIELD_FPRF 0x38000000 // 0011 1000 0000 0000 0000 0000 0000 0000
      45             : #define COUNTER_MASK_FPRF  0xc7ffffff // 1100 0111 1111 1111 1111 1111 1111 1111
      46             : 
      47             : #define COUNTER_FIELD_IURF 0x00003800 // 0000 0000 0000 0000 0011 1000 0000 0000
      48             : #define COUNTER_MASK_IURF  0xffffc7ff // 1111 1111 1111 1111 1100 0111 1111 1111
      49             : 
      50             : volatile unsigned int* asr16Ptr = (volatile unsigned int*)ASR16_REG_ADDRESS;
      51             : 
      52             : 
      53             : //***************************
      54             : // CCR Cache control register
      55             : 
      56             : static unsigned int CCR_getValue()
      57             : {
      58           4 :     unsigned int cacheControlRegister = 0;
      59           4 :     __asm__ __volatile__("lda [%%g0] 2, %0" : "=r"(cacheControlRegister) :);
      60           4 :     return cacheControlRegister;
      61             : }
      62             : 
      63             : static void CCR_setValue(unsigned int cacheControlRegister)
      64             : {
      65           4 :     __asm__ __volatile__("sta %0, [%%g0] 2" : : "r"(cacheControlRegister));
      66             : }
      67             : 
      68             : static void CCR_resetCacheControlRegister()
      69             : {
      70             :     unsigned int cacheControlRegister;
      71           1 :     cacheControlRegister = 0x00;
      72             :     CCR_setValue(cacheControlRegister);
      73             : }
      74             : 
      75             : static void CCR_enableInstructionCache()
      76             : {
      77             :     // [1:0] Instruction Cache state (ICS)
      78             :     // Indicates the current data cache state according to the following: X0 = disabled, 01 =
      79             :     // frozen, 11 = enabled.
      80             :     unsigned int cacheControlRegister;
      81           1 :     cacheControlRegister = CCR_getValue();
      82           1 :     cacheControlRegister = (cacheControlRegister | 0x3);
      83             :     CCR_setValue(cacheControlRegister);
      84             : }
      85             : 
      86             : static void CCR_enableDataCache()
      87             : {
      88             :     // [3:2] Data Cache state (DCS)
      89             :     // Indicates the current data cache state according to the following: X0 = disabled, 01 =
      90             :     // frozen, 11 = enabled.
      91             :     unsigned int cacheControlRegister;
      92           1 :     cacheControlRegister = CCR_getValue();
      93           1 :     cacheControlRegister = (cacheControlRegister | 0xc);
      94             :     CCR_setValue(cacheControlRegister);
      95             : }
      96             : 
      97             : static void CCR_enableInstructionBurstFetch()
      98             : {
      99             :     // [16] Instruction burst fetch (IB). This bit enables burst fill during instruction fetch.
     100             :     unsigned int cacheControlRegister;
     101           1 :     cacheControlRegister = CCR_getValue();
     102             :     // set the bit IB to 1
     103           1 :     cacheControlRegister = (cacheControlRegister | 0x10000);
     104             :     CCR_setValue(cacheControlRegister);
     105             : }
     106             : 
     107           0 : void CCR_getInstructionAndDataErrorCounters(
     108             :     unsigned int* instructionErrorCounter, unsigned int* dataErrorCounter)
     109             : {
     110             :     // [13:12] Instruction Tag Errors (ITE) - Number of detected parity errors in the instruction
     111             :     // tag cache. Only available if fault-tolerance is enabled (FT field in this register is
     112             :     // non-zero). [11:10] Instruction Data Errors (IDE) - Number of detected parity errors in the
     113             :     // instruction data cache. Only available if fault-tolerance is enabled (FT field in this
     114             :     // register is non-zero).
     115             : 
     116             :     unsigned int cacheControlRegister;
     117             :     unsigned int iTE;
     118             :     unsigned int iDE;
     119             :     unsigned int dTE;
     120             :     unsigned int dDE;
     121             : 
     122           0 :     cacheControlRegister = CCR_getValue();
     123           0 :     iTE = (cacheControlRegister & COUNTER_FIELD_ITE) >> POS_ITE;
     124           0 :     iDE = (cacheControlRegister & COUNTER_FIELD_IDE) >> POS_IDE;
     125           0 :     dTE = (cacheControlRegister & COUNTER_FIELD_DTE) >> POS_DTE;
     126           0 :     dDE = (cacheControlRegister & COUNTER_FIELD_DDE) >> POS_DDE;
     127             : 
     128           0 :     *instructionErrorCounter = iTE + iDE;
     129           0 :     *dataErrorCounter = dTE + dDE;
     130             : 
     131             :     // reset counters
     132           0 :     cacheControlRegister = cacheControlRegister & COUNTER_FIELD_ITE & COUNTER_FIELD_IDE
     133             :         & COUNTER_FIELD_DTE & COUNTER_FIELD_DDE;
     134             : 
     135             :     CCR_setValue(cacheControlRegister);
     136           0 : }
     137             : 
     138             : //*******************************************
     139             : // ASR16 Register protection control register
     140             : 
     141             : static void ASR16_resetRegisterProtectionControlRegister()
     142             : {
     143           1 :     *asr16Ptr = 0x00;
     144             : }
     145             : 
     146           0 : void ASR16_get_FPRF_IURF_ErrorCounters(
     147             :     unsigned int* fprfErrorCounter, unsigned int* iurfErrorCounter)
     148             : {
     149             :     /** This function is used to retrieve the integer unit register file error counter and the
     150             :      * floating point unit register file error counter
     151             :      *
     152             :      * @return void
     153             :      *
     154             :      * [29:27] FP RF error counter - Number of detected parity errors in the FP register file.
     155             :      * [13:11] IU RF error counter - Number of detected parity errors in the IU register file.
     156             :      *
     157             :      */
     158             : 
     159             :     unsigned int asr16;
     160             : 
     161           0 :     asr16 = *asr16Ptr;
     162           0 :     *fprfErrorCounter = (asr16 & COUNTER_FIELD_FPRF) >> POS_FPRF;
     163           0 :     *iurfErrorCounter = (asr16 & COUNTER_FIELD_IURF) >> POS_IURF;
     164             : 
     165             :     // reset the counter to 0
     166           0 :     asr16 = asr16 & COUNTER_MASK_FPRF & COUNTER_FIELD_IURF;
     167             : 
     168           0 :     *asr16Ptr = asr16;
     169           0 : }
     170             : 
     171           1 : static void faultTolerantScheme()
     172             : {
     173             :     // [20:19] FT scheme (FT) - “00” = no FT, “01” = 4-bit checking implemented
     174             :     unsigned int cacheControlRegister;
     175           1 :     const unsigned int* const plugAndPlayRegister=(unsigned int*)REGS_ADDR_PLUGANDPLAY;
     176           1 :     const unsigned int vendorId = ((*plugAndPlayRegister) & 0xff000000) >> 24;
     177           1 :     const unsigned int deviceId = ((*plugAndPlayRegister) & 0x00fff000) >> 12;
     178             : 
     179           1 :     cacheControlRegister = CCR_getValue();
     180             : 
     181           1 :     if ((vendorId == VENDORID_GAISLER) & (deviceId == DEVICEID_LEON3FT))
     182             :     {
     183             :         LFR_PRINTF("in faultTolerantScheme *** Leon3FT detected\n");
     184             :         LFR_PRINTF(
     185             :             "                       *** vendorID = 0x%x, deviceId = 0x%x\n", vendorId, deviceId);
     186             :         LFR_PRINTF("ASR16 IU RF protection, bit 0  (IDI) is: 0x%x (0 => protection enabled)\n",
     187             :             (*asr16Ptr >> POS_IDI) & 1);
     188             :         LFR_PRINTF("ASR16 FP RF protection, bit 16 (FDI) is: 0x%x (0 => protection enabled)\n",
     189             :             (*asr16Ptr >> POS_FDI) & 1);
     190             :         LFR_PRINTF("ASR16 IU FT ID bits [15:14] is: 0x%x (2 => 8-bit parity without restart)\n",
     191             :             (*asr16Ptr >> POS_IUFTID) & 0x3);
     192             :         LFR_PRINTF("ASR16 FP FT ID bits [31:30] is: 0x%x (1 => 4-bit parity with restart)\n",
     193             :             (*asr16Ptr >> POS_FPFTID) & 0x03);
     194             :         LFR_PRINTF("CCR   FT bits [20:19] are: 0x%x (1 => 4-bit parity with restart)\n",
     195             :             (cacheControlRegister >> POS_FT) & 0x3);
     196             : 
     197             :         // CCR The FFT bits are just read, the FT scheme is set to “01” = 4-bit checking implemented
     198             :         // by default
     199             : 
     200             :         // ASR16 Ancillary State Register configuration (Register protection control register)
     201             :         // IU RF protection is set by default, bit 0 IDI = 0
     202             :         // FP RF protection is set by default, bit 16 FDI = 0
     203             :     }
     204             :     else
     205             :     {
     206             :         LFR_PRINTF("in faultTolerantScheme *** Leon3FT not detected\n");
     207             :         LFR_PRINTF(
     208             :             "                       *** vendorID = 0x%x, deviceId = 0x%x\n", vendorId, deviceId);
     209             :     }
     210           1 : }
     211             : 
     212             : #endif /* GSCMEMORY_HPP_ */

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