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</head>
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<body>
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<table width="100%" border="0" cellspacing="0" cellpadding="0">
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<tr><td class="title">GCC Code Coverage Report</td></tr>
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<tr><td class="hr"></td></tr>
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<tr>
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<td width="100%">
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<table cellpadding="1" border="0" width="100%">
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<tr>
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<td width="10%" class="headerName">Directory:</td>
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<td width="35%" class="headerValue">./</td>
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<td width="5%"></td>
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<td width="15%"></td>
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<td width="10%" class="headerValue" style="text-align:right;">Exec</td>
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<td width="10%" class="headerValue" style="text-align:right;">Total</td>
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<td width="15%" class="headerValue" style="text-align:right;">Coverage</td>
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</tr>
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<tr>
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<td class="headerName">File:</td>
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<td class="headerValue">src/../header/GscMemoryLPP.hpp</td>
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<td></td>
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<td class="headerName">Lines:</td>
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<td class="headerTableEntry">36</td>
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<td class="headerTableEntry">52</td>
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<td class="headerTableEntry" style="background-color:LightPink">69.2 %</td>
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</tr>
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<tr>
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<td class="headerName">Date:</td>
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<td class="headerValue">2018-11-13 15:31:29</td>
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<td></td>
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<td class="headerName">Branches:</td>
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<td class="headerTableEntry">0</td>
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<td class="headerTableEntry">0</td>
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<td class="headerTableEntry" style="background-color:LightGray">- %</td>
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</tr>
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</table>
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</td>
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</tr>
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<tr><td class="hr"></td></tr>
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</table>
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<br>
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<table cellspacing="0" cellpadding="1">
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<tr>
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<td width="5%" align="right" class="srcHeader">Line</td>
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<td width="5%" align="right" class="srcHeader">Branch</td>
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<td width="5%" align="right" class="srcHeader">Exec</td>
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<td width="75%" align="left" class="srcHeader src">Source</td>
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</tr>
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<tr>
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<td align="right" class="lineno"><pre>1</pre></td>
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<td align="right" class="linebranch"></td>
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<td align="right" class="linecount "><pre></pre></td>
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<td align="left" class="src "><pre>#ifndef GSCMEMORY_HPP_</pre></td>
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</tr>
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309
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<tr>
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<td align="right" class="lineno"><pre>2</pre></td>
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<td align="right" class="linebranch"></td>
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<td align="right" class="linecount "><pre></pre></td>
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<td align="left" class="src "><pre>#define GSCMEMORY_HPP_</pre></td>
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</tr>
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<tr>
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<td align="right" class="lineno"><pre>3</pre></td>
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<td align="right" class="linebranch"></td>
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<td align="right" class="linecount "><pre></pre></td>
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320
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<td align="left" class="src "><pre></pre></td>
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321
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</tr>
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<tr>
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<td align="right" class="lineno"><pre>4</pre></td>
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<td align="right" class="linebranch"></td>
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326
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<td align="right" class="linecount "><pre></pre></td>
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327
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<td align="left" class="src "><pre>#ifndef LEON3</pre></td>
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</tr>
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<tr>
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<td align="right" class="lineno"><pre>5</pre></td>
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<td align="right" class="linebranch"></td>
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333
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<td align="right" class="linecount "><pre></pre></td>
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334
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<td align="left" class="src "><pre>#define LEON3</pre></td>
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</tr>
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<tr>
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<td align="right" class="lineno"><pre>6</pre></td>
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<td align="right" class="linebranch"></td>
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<td align="right" class="linecount "><pre></pre></td>
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<td align="left" class="src "><pre>#endif</pre></td>
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</tr>
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<tr>
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345
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<td align="right" class="lineno"><pre>7</pre></td>
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<td align="right" class="linebranch"></td>
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347
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<td align="right" class="linecount "><pre></pre></td>
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348
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<td align="left" class="src "><pre></pre></td>
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349
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</tr>
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<tr>
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352
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<td align="right" class="lineno"><pre>8</pre></td>
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<td align="right" class="linebranch"></td>
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354
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<td align="right" class="linecount "><pre></pre></td>
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355
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<td align="left" class="src "><pre>#define REGS_ADDR_PLUGANDPLAY 0xFFFFF000</pre></td>
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356
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</tr>
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<tr>
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359
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<td align="right" class="lineno"><pre>9</pre></td>
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<td align="right" class="linebranch"></td>
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361
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<td align="right" class="linecount "><pre></pre></td>
|
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362
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<td align="left" class="src "><pre>#define ASR16_REG_ADDRESS 0x90400040 // Ancillary State Register 16 = Register protection control register (FT only)</pre></td>
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</tr>
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<tr>
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<td align="right" class="lineno"><pre>10</pre></td>
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<td align="right" class="linebranch"></td>
|
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368
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<td align="right" class="linecount "><pre></pre></td>
|
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369
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<td align="left" class="src "><pre></pre></td>
|
|
370
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</tr>
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372
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<tr>
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373
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<td align="right" class="lineno"><pre>11</pre></td>
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<td align="right" class="linebranch"></td>
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375
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<td align="right" class="linecount "><pre></pre></td>
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376
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<td align="left" class="src "><pre>#define DEVICEID_LEON3 0x003</pre></td>
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377
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</tr>
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379
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<tr>
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380
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<td align="right" class="lineno"><pre>12</pre></td>
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381
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<td align="right" class="linebranch"></td>
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382
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<td align="right" class="linecount "><pre></pre></td>
|
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383
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<td align="left" class="src "><pre>#define DEVICEID_LEON3FT 0x053</pre></td>
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384
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</tr>
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385
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386
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<tr>
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387
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<td align="right" class="lineno"><pre>13</pre></td>
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<td align="right" class="linebranch"></td>
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389
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<td align="right" class="linecount "><pre></pre></td>
|
|
390
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<td align="left" class="src "><pre>#define VENDORID_GAISLER 0x01</pre></td>
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391
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</tr>
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<tr>
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<td align="right" class="lineno"><pre>14</pre></td>
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<td align="right" class="linebranch"></td>
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396
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<td align="right" class="linecount "><pre></pre></td>
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397
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<td align="left" class="src "><pre></pre></td>
|
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398
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</tr>
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399
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400
|
<tr>
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401
|
<td align="right" class="lineno"><pre>15</pre></td>
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402
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<td align="right" class="linebranch"></td>
|
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403
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<td align="right" class="linecount "><pre></pre></td>
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404
|
<td align="left" class="src "><pre>// CCR</pre></td>
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|
405
|
</tr>
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406
|
|
|
407
|
<tr>
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408
|
<td align="right" class="lineno"><pre>16</pre></td>
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409
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<td align="right" class="linebranch"></td>
|
|
410
|
<td align="right" class="linecount "><pre></pre></td>
|
|
411
|
<td align="left" class="src "><pre>#define POS_FT 19</pre></td>
|
|
412
|
</tr>
|
|
413
|
|
|
414
|
<tr>
|
|
415
|
<td align="right" class="lineno"><pre>17</pre></td>
|
|
416
|
<td align="right" class="linebranch"></td>
|
|
417
|
<td align="right" class="linecount "><pre></pre></td>
|
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418
|
<td align="left" class="src "><pre>//</pre></td>
|
|
419
|
</tr>
|
|
420
|
|
|
421
|
<tr>
|
|
422
|
<td align="right" class="lineno"><pre>18</pre></td>
|
|
423
|
<td align="right" class="linebranch"></td>
|
|
424
|
<td align="right" class="linecount "><pre></pre></td>
|
|
425
|
<td align="left" class="src "><pre>#define POS_ITE 12</pre></td>
|
|
426
|
</tr>
|
|
427
|
|
|
428
|
<tr>
|
|
429
|
<td align="right" class="lineno"><pre>19</pre></td>
|
|
430
|
<td align="right" class="linebranch"></td>
|
|
431
|
<td align="right" class="linecount "><pre></pre></td>
|
|
432
|
<td align="left" class="src "><pre>#define COUNTER_FIELD_ITE 0x00003000 // 0000 0000 0000 0000 0011 0000 0000 0000</pre></td>
|
|
433
|
</tr>
|
|
434
|
|
|
435
|
<tr>
|
|
436
|
<td align="right" class="lineno"><pre>20</pre></td>
|
|
437
|
<td align="right" class="linebranch"></td>
|
|
438
|
<td align="right" class="linecount "><pre></pre></td>
|
|
439
|
<td align="left" class="src "><pre>#define COUNTER_MASK_ITE 0xffffcfff // 1111 1111 1111 1111 1100 1111 1111 1111</pre></td>
|
|
440
|
</tr>
|
|
441
|
|
|
442
|
<tr>
|
|
443
|
<td align="right" class="lineno"><pre>21</pre></td>
|
|
444
|
<td align="right" class="linebranch"></td>
|
|
445
|
<td align="right" class="linecount "><pre></pre></td>
|
|
446
|
<td align="left" class="src "><pre>#define POS_IDE 10</pre></td>
|
|
447
|
</tr>
|
|
448
|
|
|
449
|
<tr>
|
|
450
|
<td align="right" class="lineno"><pre>22</pre></td>
|
|
451
|
<td align="right" class="linebranch"></td>
|
|
452
|
<td align="right" class="linecount "><pre></pre></td>
|
|
453
|
<td align="left" class="src "><pre>#define COUNTER_FIELD_IDE 0x00000c00 // 0000 0000 0000 0000 0000 1100 0000 0000</pre></td>
|
|
454
|
</tr>
|
|
455
|
|
|
456
|
<tr>
|
|
457
|
<td align="right" class="lineno"><pre>23</pre></td>
|
|
458
|
<td align="right" class="linebranch"></td>
|
|
459
|
<td align="right" class="linecount "><pre></pre></td>
|
|
460
|
<td align="left" class="src "><pre>#define COUNTER_MASK_IDE 0xfffff3ff // 1111 1111 1111 1111 1111 0011 1111 1111</pre></td>
|
|
461
|
</tr>
|
|
462
|
|
|
463
|
<tr>
|
|
464
|
<td align="right" class="lineno"><pre>24</pre></td>
|
|
465
|
<td align="right" class="linebranch"></td>
|
|
466
|
<td align="right" class="linecount "><pre></pre></td>
|
|
467
|
<td align="left" class="src "><pre>//</pre></td>
|
|
468
|
</tr>
|
|
469
|
|
|
470
|
<tr>
|
|
471
|
<td align="right" class="lineno"><pre>25</pre></td>
|
|
472
|
<td align="right" class="linebranch"></td>
|
|
473
|
<td align="right" class="linecount "><pre></pre></td>
|
|
474
|
<td align="left" class="src "><pre>#define POS_DTE 8</pre></td>
|
|
475
|
</tr>
|
|
476
|
|
|
477
|
<tr>
|
|
478
|
<td align="right" class="lineno"><pre>26</pre></td>
|
|
479
|
<td align="right" class="linebranch"></td>
|
|
480
|
<td align="right" class="linecount "><pre></pre></td>
|
|
481
|
<td align="left" class="src "><pre>#define COUNTER_FIELD_DTE 0x00000300 // 0000 0000 0000 0000 0000 0011 0000 0000</pre></td>
|
|
482
|
</tr>
|
|
483
|
|
|
484
|
<tr>
|
|
485
|
<td align="right" class="lineno"><pre>27</pre></td>
|
|
486
|
<td align="right" class="linebranch"></td>
|
|
487
|
<td align="right" class="linecount "><pre></pre></td>
|
|
488
|
<td align="left" class="src "><pre>#define COUNTER_MASK_DTE 0xfffffcff // 1111 1111 1111 1111 1111 1100 1111 1111</pre></td>
|
|
489
|
</tr>
|
|
490
|
|
|
491
|
<tr>
|
|
492
|
<td align="right" class="lineno"><pre>28</pre></td>
|
|
493
|
<td align="right" class="linebranch"></td>
|
|
494
|
<td align="right" class="linecount "><pre></pre></td>
|
|
495
|
<td align="left" class="src "><pre>#define POS_DDE 6</pre></td>
|
|
496
|
</tr>
|
|
497
|
|
|
498
|
<tr>
|
|
499
|
<td align="right" class="lineno"><pre>29</pre></td>
|
|
500
|
<td align="right" class="linebranch"></td>
|
|
501
|
<td align="right" class="linecount "><pre></pre></td>
|
|
502
|
<td align="left" class="src "><pre>#define COUNTER_FIELD_DDE 0x000000c0 // 0000 0000 0000 0000 0000 0000 1100 0000</pre></td>
|
|
503
|
</tr>
|
|
504
|
|
|
505
|
<tr>
|
|
506
|
<td align="right" class="lineno"><pre>30</pre></td>
|
|
507
|
<td align="right" class="linebranch"></td>
|
|
508
|
<td align="right" class="linecount "><pre></pre></td>
|
|
509
|
<td align="left" class="src "><pre>#define COUNTER_MASK_DDE 0xffffff3f // 1111 1111 1111 1111 1111 1111 0011 1111</pre></td>
|
|
510
|
</tr>
|
|
511
|
|
|
512
|
<tr>
|
|
513
|
<td align="right" class="lineno"><pre>31</pre></td>
|
|
514
|
<td align="right" class="linebranch"></td>
|
|
515
|
<td align="right" class="linecount "><pre></pre></td>
|
|
516
|
<td align="left" class="src "><pre></pre></td>
|
|
517
|
</tr>
|
|
518
|
|
|
519
|
<tr>
|
|
520
|
<td align="right" class="lineno"><pre>32</pre></td>
|
|
521
|
<td align="right" class="linebranch"></td>
|
|
522
|
<td align="right" class="linecount "><pre></pre></td>
|
|
523
|
<td align="left" class="src "><pre>// ASR16</pre></td>
|
|
524
|
</tr>
|
|
525
|
|
|
526
|
<tr>
|
|
527
|
<td align="right" class="lineno"><pre>33</pre></td>
|
|
528
|
<td align="right" class="linebranch"></td>
|
|
529
|
<td align="right" class="linecount "><pre></pre></td>
|
|
530
|
<td align="left" class="src "><pre>#define POS_FPFTID 30</pre></td>
|
|
531
|
</tr>
|
|
532
|
|
|
533
|
<tr>
|
|
534
|
<td align="right" class="lineno"><pre>34</pre></td>
|
|
535
|
<td align="right" class="linebranch"></td>
|
|
536
|
<td align="right" class="linecount "><pre></pre></td>
|
|
537
|
<td align="left" class="src "><pre>#define POS_FPRF 27</pre></td>
|
|
538
|
</tr>
|
|
539
|
|
|
540
|
<tr>
|
|
541
|
<td align="right" class="lineno"><pre>35</pre></td>
|
|
542
|
<td align="right" class="linebranch"></td>
|
|
543
|
<td align="right" class="linecount "><pre></pre></td>
|
|
544
|
<td align="left" class="src "><pre>#define POS_FDI 16 // FP RF protection enable/disable</pre></td>
|
|
545
|
</tr>
|
|
546
|
|
|
547
|
<tr>
|
|
548
|
<td align="right" class="lineno"><pre>36</pre></td>
|
|
549
|
<td align="right" class="linebranch"></td>
|
|
550
|
<td align="right" class="linecount "><pre></pre></td>
|
|
551
|
<td align="left" class="src "><pre>#define POS_IUFTID 14</pre></td>
|
|
552
|
</tr>
|
|
553
|
|
|
554
|
<tr>
|
|
555
|
<td align="right" class="lineno"><pre>37</pre></td>
|
|
556
|
<td align="right" class="linebranch"></td>
|
|
557
|
<td align="right" class="linecount "><pre></pre></td>
|
|
558
|
<td align="left" class="src "><pre>#define POS_IURF 11</pre></td>
|
|
559
|
</tr>
|
|
560
|
|
|
561
|
<tr>
|
|
562
|
<td align="right" class="lineno"><pre>38</pre></td>
|
|
563
|
<td align="right" class="linebranch"></td>
|
|
564
|
<td align="right" class="linecount "><pre></pre></td>
|
|
565
|
<td align="left" class="src "><pre>#define POS_IDI 0 // IU RF protection enable/disable</pre></td>
|
|
566
|
</tr>
|
|
567
|
|
|
568
|
<tr>
|
|
569
|
<td align="right" class="lineno"><pre>39</pre></td>
|
|
570
|
<td align="right" class="linebranch"></td>
|
|
571
|
<td align="right" class="linecount "><pre></pre></td>
|
|
572
|
<td align="left" class="src "><pre></pre></td>
|
|
573
|
</tr>
|
|
574
|
|
|
575
|
<tr>
|
|
576
|
<td align="right" class="lineno"><pre>40</pre></td>
|
|
577
|
<td align="right" class="linebranch"></td>
|
|
578
|
<td align="right" class="linecount "><pre></pre></td>
|
|
579
|
<td align="left" class="src "><pre>#define COUNTER_FIELD_FPRF 0x38000000 // 0011 1000 0000 0000 0000 0000 0000 0000</pre></td>
|
|
580
|
</tr>
|
|
581
|
|
|
582
|
<tr>
|
|
583
|
<td align="right" class="lineno"><pre>41</pre></td>
|
|
584
|
<td align="right" class="linebranch"></td>
|
|
585
|
<td align="right" class="linecount "><pre></pre></td>
|
|
586
|
<td align="left" class="src "><pre>#define COUNTER_MASK_FPRF 0xc7ffffff // 1100 0111 1111 1111 1111 1111 1111 1111</pre></td>
|
|
587
|
</tr>
|
|
588
|
|
|
589
|
<tr>
|
|
590
|
<td align="right" class="lineno"><pre>42</pre></td>
|
|
591
|
<td align="right" class="linebranch"></td>
|
|
592
|
<td align="right" class="linecount "><pre></pre></td>
|
|
593
|
<td align="left" class="src "><pre></pre></td>
|
|
594
|
</tr>
|
|
595
|
|
|
596
|
<tr>
|
|
597
|
<td align="right" class="lineno"><pre>43</pre></td>
|
|
598
|
<td align="right" class="linebranch"></td>
|
|
599
|
<td align="right" class="linecount "><pre></pre></td>
|
|
600
|
<td align="left" class="src "><pre>#define COUNTER_FIELD_IURF 0x00003800 // 0000 0000 0000 0000 0011 1000 0000 0000</pre></td>
|
|
601
|
</tr>
|
|
602
|
|
|
603
|
<tr>
|
|
604
|
<td align="right" class="lineno"><pre>44</pre></td>
|
|
605
|
<td align="right" class="linebranch"></td>
|
|
606
|
<td align="right" class="linecount "><pre></pre></td>
|
|
607
|
<td align="left" class="src "><pre>#define COUNTER_MASK_IURF 0xffffc7ff // 1111 1111 1111 1111 1100 0111 1111 1111</pre></td>
|
|
608
|
</tr>
|
|
609
|
|
|
610
|
<tr>
|
|
611
|
<td align="right" class="lineno"><pre>45</pre></td>
|
|
612
|
<td align="right" class="linebranch"></td>
|
|
613
|
<td align="right" class="linecount "><pre></pre></td>
|
|
614
|
<td align="left" class="src "><pre></pre></td>
|
|
615
|
</tr>
|
|
616
|
|
|
617
|
<tr>
|
|
618
|
<td align="right" class="lineno"><pre>46</pre></td>
|
|
619
|
<td align="right" class="linebranch"></td>
|
|
620
|
<td align="right" class="linecount "><pre></pre></td>
|
|
621
|
<td align="left" class="src "><pre>volatile unsigned int *asr16Ptr = (volatile unsigned int *) ASR16_REG_ADDRESS;</pre></td>
|
|
622
|
</tr>
|
|
623
|
|
|
624
|
<tr>
|
|
625
|
<td align="right" class="lineno"><pre>47</pre></td>
|
|
626
|
<td align="right" class="linebranch"></td>
|
|
627
|
<td align="right" class="linecount "><pre></pre></td>
|
|
628
|
<td align="left" class="src "><pre>#ifdef ENABLE_DEAD_CODE</pre></td>
|
|
629
|
</tr>
|
|
630
|
|
|
631
|
<tr>
|
|
632
|
<td align="right" class="lineno"><pre>48</pre></td>
|
|
633
|
<td align="right" class="linebranch"></td>
|
|
634
|
<td align="right" class="linecount "><pre></pre></td>
|
|
635
|
<td align="left" class="src "><pre>static inline void flushCache()</pre></td>
|
|
636
|
</tr>
|
|
637
|
|
|
638
|
<tr>
|
|
639
|
<td align="right" class="lineno"><pre>49</pre></td>
|
|
640
|
<td align="right" class="linebranch"></td>
|
|
641
|
<td align="right" class="linecount "><pre></pre></td>
|
|
642
|
<td align="left" class="src "><pre>{</pre></td>
|
|
643
|
</tr>
|
|
644
|
|
|
645
|
<tr>
|
|
646
|
<td align="right" class="lineno"><pre>50</pre></td>
|
|
647
|
<td align="right" class="linebranch"></td>
|
|
648
|
<td align="right" class="linecount "><pre></pre></td>
|
|
649
|
<td align="left" class="src "><pre> /**</pre></td>
|
|
650
|
</tr>
|
|
651
|
|
|
652
|
<tr>
|
|
653
|
<td align="right" class="lineno"><pre>51</pre></td>
|
|
654
|
<td align="right" class="linebranch"></td>
|
|
655
|
<td align="right" class="linecount "><pre></pre></td>
|
|
656
|
<td align="left" class="src "><pre> * Flush the data cache and the instruction cache.</pre></td>
|
|
657
|
</tr>
|
|
658
|
|
|
659
|
<tr>
|
|
660
|
<td align="right" class="lineno"><pre>52</pre></td>
|
|
661
|
<td align="right" class="linebranch"></td>
|
|
662
|
<td align="right" class="linecount "><pre></pre></td>
|
|
663
|
<td align="left" class="src "><pre> *</pre></td>
|
|
664
|
</tr>
|
|
665
|
|
|
666
|
<tr>
|
|
667
|
<td align="right" class="lineno"><pre>53</pre></td>
|
|
668
|
<td align="right" class="linebranch"></td>
|
|
669
|
<td align="right" class="linecount "><pre></pre></td>
|
|
670
|
<td align="left" class="src "><pre> * @param void</pre></td>
|
|
671
|
</tr>
|
|
672
|
|
|
673
|
<tr>
|
|
674
|
<td align="right" class="lineno"><pre>54</pre></td>
|
|
675
|
<td align="right" class="linebranch"></td>
|
|
676
|
<td align="right" class="linecount "><pre></pre></td>
|
|
677
|
<td align="left" class="src "><pre> *</pre></td>
|
|
678
|
</tr>
|
|
679
|
|
|
680
|
<tr>
|
|
681
|
<td align="right" class="lineno"><pre>55</pre></td>
|
|
682
|
<td align="right" class="linebranch"></td>
|
|
683
|
<td align="right" class="linecount "><pre></pre></td>
|
|
684
|
<td align="left" class="src "><pre> * @return void</pre></td>
|
|
685
|
</tr>
|
|
686
|
|
|
687
|
<tr>
|
|
688
|
<td align="right" class="lineno"><pre>56</pre></td>
|
|
689
|
<td align="right" class="linebranch"></td>
|
|
690
|
<td align="right" class="linecount "><pre></pre></td>
|
|
691
|
<td align="left" class="src "><pre> */</pre></td>
|
|
692
|
</tr>
|
|
693
|
|
|
694
|
<tr>
|
|
695
|
<td align="right" class="lineno"><pre>57</pre></td>
|
|
696
|
<td align="right" class="linebranch"></td>
|
|
697
|
<td align="right" class="linecount "><pre></pre></td>
|
|
698
|
<td align="left" class="src "><pre></pre></td>
|
|
699
|
</tr>
|
|
700
|
|
|
701
|
<tr>
|
|
702
|
<td align="right" class="lineno"><pre>58</pre></td>
|
|
703
|
<td align="right" class="linebranch"></td>
|
|
704
|
<td align="right" class="linecount "><pre></pre></td>
|
|
705
|
<td align="left" class="src "><pre> asm("flush");</pre></td>
|
|
706
|
</tr>
|
|
707
|
|
|
708
|
<tr>
|
|
709
|
<td align="right" class="lineno"><pre>59</pre></td>
|
|
710
|
<td align="right" class="linebranch"></td>
|
|
711
|
<td align="right" class="linecount "><pre></pre></td>
|
|
712
|
<td align="left" class="src "><pre>}</pre></td>
|
|
713
|
</tr>
|
|
714
|
|
|
715
|
<tr>
|
|
716
|
<td align="right" class="lineno"><pre>60</pre></td>
|
|
717
|
<td align="right" class="linebranch"></td>
|
|
718
|
<td align="right" class="linecount "><pre></pre></td>
|
|
719
|
<td align="left" class="src "><pre>#endif</pre></td>
|
|
720
|
</tr>
|
|
721
|
|
|
722
|
<tr>
|
|
723
|
<td align="right" class="lineno"><pre>61</pre></td>
|
|
724
|
<td align="right" class="linebranch"></td>
|
|
725
|
<td align="right" class="linecount "><pre></pre></td>
|
|
726
|
<td align="left" class="src "><pre></pre></td>
|
|
727
|
</tr>
|
|
728
|
|
|
729
|
<tr>
|
|
730
|
<td align="right" class="lineno"><pre>62</pre></td>
|
|
731
|
<td align="right" class="linebranch"></td>
|
|
732
|
<td align="right" class="linecount "><pre></pre></td>
|
|
733
|
<td align="left" class="src "><pre>//***************************</pre></td>
|
|
734
|
</tr>
|
|
735
|
|
|
736
|
<tr>
|
|
737
|
<td align="right" class="lineno"><pre>63</pre></td>
|
|
738
|
<td align="right" class="linebranch"></td>
|
|
739
|
<td align="right" class="linecount "><pre></pre></td>
|
|
740
|
<td align="left" class="src "><pre>// CCR Cache control register</pre></td>
|
|
741
|
</tr>
|
|
742
|
|
|
743
|
<tr>
|
|
744
|
<td align="right" class="lineno"><pre>64</pre></td>
|
|
745
|
<td align="right" class="linebranch"></td>
|
|
746
|
<td align="right" class="linecount "><pre></pre></td>
|
|
747
|
<td align="left" class="src "><pre></pre></td>
|
|
748
|
</tr>
|
|
749
|
|
|
750
|
<tr>
|
|
751
|
<td align="right" class="lineno"><pre>65</pre></td>
|
|
752
|
<td align="right" class="linebranch"></td>
|
|
753
|
<td align="right" class="linecount coveredLine"><pre>6</pre></td>
|
|
754
|
<td align="left" class="src coveredLine"><pre>static unsigned int CCR_getValue()</pre></td>
|
|
755
|
</tr>
|
|
756
|
|
|
757
|
<tr>
|
|
758
|
<td align="right" class="lineno"><pre>66</pre></td>
|
|
759
|
<td align="right" class="linebranch"></td>
|
|
760
|
<td align="right" class="linecount "><pre></pre></td>
|
|
761
|
<td align="left" class="src "><pre>{</pre></td>
|
|
762
|
</tr>
|
|
763
|
|
|
764
|
<tr>
|
|
765
|
<td align="right" class="lineno"><pre>67</pre></td>
|
|
766
|
<td align="right" class="linebranch"></td>
|
|
767
|
<td align="right" class="linecount coveredLine"><pre>6</pre></td>
|
|
768
|
<td align="left" class="src coveredLine"><pre> unsigned int cacheControlRegister = 0;</pre></td>
|
|
769
|
</tr>
|
|
770
|
|
|
771
|
<tr>
|
|
772
|
<td align="right" class="lineno"><pre>68</pre></td>
|
|
773
|
<td align="right" class="linebranch"></td>
|
|
774
|
<td align="right" class="linecount coveredLine"><pre>6</pre></td>
|
|
775
|
<td align="left" class="src coveredLine"><pre> __asm__ __volatile__("lda [%%g0] 2, %0" : "=r"(cacheControlRegister) : );</pre></td>
|
|
776
|
</tr>
|
|
777
|
|
|
778
|
<tr>
|
|
779
|
<td align="right" class="lineno"><pre>69</pre></td>
|
|
780
|
<td align="right" class="linebranch"></td>
|
|
781
|
<td align="right" class="linecount coveredLine"><pre>6</pre></td>
|
|
782
|
<td align="left" class="src coveredLine"><pre> return cacheControlRegister;</pre></td>
|
|
783
|
</tr>
|
|
784
|
|
|
785
|
<tr>
|
|
786
|
<td align="right" class="lineno"><pre>70</pre></td>
|
|
787
|
<td align="right" class="linebranch"></td>
|
|
788
|
<td align="right" class="linecount "><pre></pre></td>
|
|
789
|
<td align="left" class="src "><pre>}</pre></td>
|
|
790
|
</tr>
|
|
791
|
|
|
792
|
<tr>
|
|
793
|
<td align="right" class="lineno"><pre>71</pre></td>
|
|
794
|
<td align="right" class="linebranch"></td>
|
|
795
|
<td align="right" class="linecount "><pre></pre></td>
|
|
796
|
<td align="left" class="src "><pre></pre></td>
|
|
797
|
</tr>
|
|
798
|
|
|
799
|
<tr>
|
|
800
|
<td align="right" class="lineno"><pre>72</pre></td>
|
|
801
|
<td align="right" class="linebranch"></td>
|
|
802
|
<td align="right" class="linecount coveredLine"><pre>4</pre></td>
|
|
803
|
<td align="left" class="src coveredLine"><pre>static void CCR_setValue(unsigned int cacheControlRegister)</pre></td>
|
|
804
|
</tr>
|
|
805
|
|
|
806
|
<tr>
|
|
807
|
<td align="right" class="lineno"><pre>73</pre></td>
|
|
808
|
<td align="right" class="linebranch"></td>
|
|
809
|
<td align="right" class="linecount "><pre></pre></td>
|
|
810
|
<td align="left" class="src "><pre>{</pre></td>
|
|
811
|
</tr>
|
|
812
|
|
|
813
|
<tr>
|
|
814
|
<td align="right" class="lineno"><pre>74</pre></td>
|
|
815
|
<td align="right" class="linebranch"></td>
|
|
816
|
<td align="right" class="linecount coveredLine"><pre>4</pre></td>
|
|
817
|
<td align="left" class="src coveredLine"><pre> __asm__ __volatile__("sta %0, [%%g0] 2" : : "r"(cacheControlRegister));</pre></td>
|
|
818
|
</tr>
|
|
819
|
|
|
820
|
<tr>
|
|
821
|
<td align="right" class="lineno"><pre>75</pre></td>
|
|
822
|
<td align="right" class="linebranch"></td>
|
|
823
|
<td align="right" class="linecount coveredLine"><pre>4</pre></td>
|
|
824
|
<td align="left" class="src coveredLine"><pre>}</pre></td>
|
|
825
|
</tr>
|
|
826
|
|
|
827
|
<tr>
|
|
828
|
<td align="right" class="lineno"><pre>76</pre></td>
|
|
829
|
<td align="right" class="linebranch"></td>
|
|
830
|
<td align="right" class="linecount "><pre></pre></td>
|
|
831
|
<td align="left" class="src "><pre></pre></td>
|
|
832
|
</tr>
|
|
833
|
|
|
834
|
<tr>
|
|
835
|
<td align="right" class="lineno"><pre>77</pre></td>
|
|
836
|
<td align="right" class="linebranch"></td>
|
|
837
|
<td align="right" class="linecount coveredLine"><pre>1</pre></td>
|
|
838
|
<td align="left" class="src coveredLine"><pre>static void CCR_resetCacheControlRegister()</pre></td>
|
|
839
|
</tr>
|
|
840
|
|
|
841
|
<tr>
|
|
842
|
<td align="right" class="lineno"><pre>78</pre></td>
|
|
843
|
<td align="right" class="linebranch"></td>
|
|
844
|
<td align="right" class="linecount "><pre></pre></td>
|
|
845
|
<td align="left" class="src "><pre>{</pre></td>
|
|
846
|
</tr>
|
|
847
|
|
|
848
|
<tr>
|
|
849
|
<td align="right" class="lineno"><pre>79</pre></td>
|
|
850
|
<td align="right" class="linebranch"></td>
|
|
851
|
<td align="right" class="linecount "><pre></pre></td>
|
|
852
|
<td align="left" class="src "><pre> unsigned int cacheControlRegister;</pre></td>
|
|
853
|
</tr>
|
|
854
|
|
|
855
|
<tr>
|
|
856
|
<td align="right" class="lineno"><pre>80</pre></td>
|
|
857
|
<td align="right" class="linebranch"></td>
|
|
858
|
<td align="right" class="linecount coveredLine"><pre>1</pre></td>
|
|
859
|
<td align="left" class="src coveredLine"><pre> cacheControlRegister = 0x00;</pre></td>
|
|
860
|
</tr>
|
|
861
|
|
|
862
|
<tr>
|
|
863
|
<td align="right" class="lineno"><pre>81</pre></td>
|
|
864
|
<td align="right" class="linebranch"></td>
|
|
865
|
<td align="right" class="linecount coveredLine"><pre>1</pre></td>
|
|
866
|
<td align="left" class="src coveredLine"><pre> CCR_setValue(cacheControlRegister);</pre></td>
|
|
867
|
</tr>
|
|
868
|
|
|
869
|
<tr>
|
|
870
|
<td align="right" class="lineno"><pre>82</pre></td>
|
|
871
|
<td align="right" class="linebranch"></td>
|
|
872
|
<td align="right" class="linecount coveredLine"><pre>1</pre></td>
|
|
873
|
<td align="left" class="src coveredLine"><pre>}</pre></td>
|
|
874
|
</tr>
|
|
875
|
|
|
876
|
<tr>
|
|
877
|
<td align="right" class="lineno"><pre>83</pre></td>
|
|
878
|
<td align="right" class="linebranch"></td>
|
|
879
|
<td align="right" class="linecount "><pre></pre></td>
|
|
880
|
<td align="left" class="src "><pre></pre></td>
|
|
881
|
</tr>
|
|
882
|
|
|
883
|
<tr>
|
|
884
|
<td align="right" class="lineno"><pre>84</pre></td>
|
|
885
|
<td align="right" class="linebranch"></td>
|
|
886
|
<td align="right" class="linecount coveredLine"><pre>1</pre></td>
|
|
887
|
<td align="left" class="src coveredLine"><pre>static void CCR_enableInstructionCache()</pre></td>
|
|
888
|
</tr>
|
|
889
|
|
|
890
|
<tr>
|
|
891
|
<td align="right" class="lineno"><pre>85</pre></td>
|
|
892
|
<td align="right" class="linebranch"></td>
|
|
893
|
<td align="right" class="linecount "><pre></pre></td>
|
|
894
|
<td align="left" class="src "><pre>{</pre></td>
|
|
895
|
</tr>
|
|
896
|
|
|
897
|
<tr>
|
|
898
|
<td align="right" class="lineno"><pre>86</pre></td>
|
|
899
|
<td align="right" class="linebranch"></td>
|
|
900
|
<td align="right" class="linecount "><pre></pre></td>
|
|
901
|
<td align="left" class="src "><pre> // [1:0] Instruction Cache state (ICS)</pre></td>
|
|
902
|
</tr>
|
|
903
|
|
|
904
|
<tr>
|
|
905
|
<td align="right" class="lineno"><pre>87</pre></td>
|
|
906
|
<td align="right" class="linebranch"></td>
|
|
907
|
<td align="right" class="linecount "><pre></pre></td>
|
|
908
|
<td align="left" class="src "><pre> // Indicates the current data cache state according to the following: X0 = disabled, 01 = frozen, 11 = enabled.</pre></td>
|
|
909
|
</tr>
|
|
910
|
|
|
911
|
<tr>
|
|
912
|
<td align="right" class="lineno"><pre>88</pre></td>
|
|
913
|
<td align="right" class="linebranch"></td>
|
|
914
|
<td align="right" class="linecount "><pre></pre></td>
|
|
915
|
<td align="left" class="src "><pre> unsigned int cacheControlRegister;</pre></td>
|
|
916
|
</tr>
|
|
917
|
|
|
918
|
<tr>
|
|
919
|
<td align="right" class="lineno"><pre>89</pre></td>
|
|
920
|
<td align="right" class="linebranch"></td>
|
|
921
|
<td align="right" class="linecount coveredLine"><pre>1</pre></td>
|
|
922
|
<td align="left" class="src coveredLine"><pre> cacheControlRegister = CCR_getValue();</pre></td>
|
|
923
|
</tr>
|
|
924
|
|
|
925
|
<tr>
|
|
926
|
<td align="right" class="lineno"><pre>90</pre></td>
|
|
927
|
<td align="right" class="linebranch"></td>
|
|
928
|
<td align="right" class="linecount coveredLine"><pre>1</pre></td>
|
|
929
|
<td align="left" class="src coveredLine"><pre> cacheControlRegister = (cacheControlRegister | 0x3);</pre></td>
|
|
930
|
</tr>
|
|
931
|
|
|
932
|
<tr>
|
|
933
|
<td align="right" class="lineno"><pre>91</pre></td>
|
|
934
|
<td align="right" class="linebranch"></td>
|
|
935
|
<td align="right" class="linecount coveredLine"><pre>1</pre></td>
|
|
936
|
<td align="left" class="src coveredLine"><pre> CCR_setValue(cacheControlRegister);</pre></td>
|
|
937
|
</tr>
|
|
938
|
|
|
939
|
<tr>
|
|
940
|
<td align="right" class="lineno"><pre>92</pre></td>
|
|
941
|
<td align="right" class="linebranch"></td>
|
|
942
|
<td align="right" class="linecount coveredLine"><pre>1</pre></td>
|
|
943
|
<td align="left" class="src coveredLine"><pre>}</pre></td>
|
|
944
|
</tr>
|
|
945
|
|
|
946
|
<tr>
|
|
947
|
<td align="right" class="lineno"><pre>93</pre></td>
|
|
948
|
<td align="right" class="linebranch"></td>
|
|
949
|
<td align="right" class="linecount "><pre></pre></td>
|
|
950
|
<td align="left" class="src "><pre></pre></td>
|
|
951
|
</tr>
|
|
952
|
|
|
953
|
<tr>
|
|
954
|
<td align="right" class="lineno"><pre>94</pre></td>
|
|
955
|
<td align="right" class="linebranch"></td>
|
|
956
|
<td align="right" class="linecount coveredLine"><pre>1</pre></td>
|
|
957
|
<td align="left" class="src coveredLine"><pre>static void CCR_enableDataCache()</pre></td>
|
|
958
|
</tr>
|
|
959
|
|
|
960
|
<tr>
|
|
961
|
<td align="right" class="lineno"><pre>95</pre></td>
|
|
962
|
<td align="right" class="linebranch"></td>
|
|
963
|
<td align="right" class="linecount "><pre></pre></td>
|
|
964
|
<td align="left" class="src "><pre>{</pre></td>
|
|
965
|
</tr>
|
|
966
|
|
|
967
|
<tr>
|
|
968
|
<td align="right" class="lineno"><pre>96</pre></td>
|
|
969
|
<td align="right" class="linebranch"></td>
|
|
970
|
<td align="right" class="linecount "><pre></pre></td>
|
|
971
|
<td align="left" class="src "><pre> // [3:2] Data Cache state (DCS)</pre></td>
|
|
972
|
</tr>
|
|
973
|
|
|
974
|
<tr>
|
|
975
|
<td align="right" class="lineno"><pre>97</pre></td>
|
|
976
|
<td align="right" class="linebranch"></td>
|
|
977
|
<td align="right" class="linecount "><pre></pre></td>
|
|
978
|
<td align="left" class="src "><pre> // Indicates the current data cache state according to the following: X0 = disabled, 01 = frozen, 11 = enabled.</pre></td>
|
|
979
|
</tr>
|
|
980
|
|
|
981
|
<tr>
|
|
982
|
<td align="right" class="lineno"><pre>98</pre></td>
|
|
983
|
<td align="right" class="linebranch"></td>
|
|
984
|
<td align="right" class="linecount "><pre></pre></td>
|
|
985
|
<td align="left" class="src "><pre> unsigned int cacheControlRegister;</pre></td>
|
|
986
|
</tr>
|
|
987
|
|
|
988
|
<tr>
|
|
989
|
<td align="right" class="lineno"><pre>99</pre></td>
|
|
990
|
<td align="right" class="linebranch"></td>
|
|
991
|
<td align="right" class="linecount coveredLine"><pre>1</pre></td>
|
|
992
|
<td align="left" class="src coveredLine"><pre> cacheControlRegister = CCR_getValue();</pre></td>
|
|
993
|
</tr>
|
|
994
|
|
|
995
|
<tr>
|
|
996
|
<td align="right" class="lineno"><pre>100</pre></td>
|
|
997
|
<td align="right" class="linebranch"></td>
|
|
998
|
<td align="right" class="linecount coveredLine"><pre>1</pre></td>
|
|
999
|
<td align="left" class="src coveredLine"><pre> cacheControlRegister = (cacheControlRegister | 0xc);</pre></td>
|
|
1000
|
</tr>
|
|
1001
|
|
|
1002
|
<tr>
|
|
1003
|
<td align="right" class="lineno"><pre>101</pre></td>
|
|
1004
|
<td align="right" class="linebranch"></td>
|
|
1005
|
<td align="right" class="linecount coveredLine"><pre>1</pre></td>
|
|
1006
|
<td align="left" class="src coveredLine"><pre> CCR_setValue(cacheControlRegister);</pre></td>
|
|
1007
|
</tr>
|
|
1008
|
|
|
1009
|
<tr>
|
|
1010
|
<td align="right" class="lineno"><pre>102</pre></td>
|
|
1011
|
<td align="right" class="linebranch"></td>
|
|
1012
|
<td align="right" class="linecount coveredLine"><pre>1</pre></td>
|
|
1013
|
<td align="left" class="src coveredLine"><pre>}</pre></td>
|
|
1014
|
</tr>
|
|
1015
|
|
|
1016
|
<tr>
|
|
1017
|
<td align="right" class="lineno"><pre>103</pre></td>
|
|
1018
|
<td align="right" class="linebranch"></td>
|
|
1019
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1020
|
<td align="left" class="src "><pre></pre></td>
|
|
1021
|
</tr>
|
|
1022
|
|
|
1023
|
<tr>
|
|
1024
|
<td align="right" class="lineno"><pre>104</pre></td>
|
|
1025
|
<td align="right" class="linebranch"></td>
|
|
1026
|
<td align="right" class="linecount coveredLine"><pre>1</pre></td>
|
|
1027
|
<td align="left" class="src coveredLine"><pre>static void CCR_enableInstructionBurstFetch()</pre></td>
|
|
1028
|
</tr>
|
|
1029
|
|
|
1030
|
<tr>
|
|
1031
|
<td align="right" class="lineno"><pre>105</pre></td>
|
|
1032
|
<td align="right" class="linebranch"></td>
|
|
1033
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1034
|
<td align="left" class="src "><pre>{</pre></td>
|
|
1035
|
</tr>
|
|
1036
|
|
|
1037
|
<tr>
|
|
1038
|
<td align="right" class="lineno"><pre>106</pre></td>
|
|
1039
|
<td align="right" class="linebranch"></td>
|
|
1040
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1041
|
<td align="left" class="src "><pre> // [16] Instruction burst fetch (IB). This bit enables burst fill during instruction fetch.</pre></td>
|
|
1042
|
</tr>
|
|
1043
|
|
|
1044
|
<tr>
|
|
1045
|
<td align="right" class="lineno"><pre>107</pre></td>
|
|
1046
|
<td align="right" class="linebranch"></td>
|
|
1047
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1048
|
<td align="left" class="src "><pre> unsigned int cacheControlRegister;</pre></td>
|
|
1049
|
</tr>
|
|
1050
|
|
|
1051
|
<tr>
|
|
1052
|
<td align="right" class="lineno"><pre>108</pre></td>
|
|
1053
|
<td align="right" class="linebranch"></td>
|
|
1054
|
<td align="right" class="linecount coveredLine"><pre>1</pre></td>
|
|
1055
|
<td align="left" class="src coveredLine"><pre> cacheControlRegister = CCR_getValue();</pre></td>
|
|
1056
|
</tr>
|
|
1057
|
|
|
1058
|
<tr>
|
|
1059
|
<td align="right" class="lineno"><pre>109</pre></td>
|
|
1060
|
<td align="right" class="linebranch"></td>
|
|
1061
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1062
|
<td align="left" class="src "><pre> // set the bit IB to 1</pre></td>
|
|
1063
|
</tr>
|
|
1064
|
|
|
1065
|
<tr>
|
|
1066
|
<td align="right" class="lineno"><pre>110</pre></td>
|
|
1067
|
<td align="right" class="linebranch"></td>
|
|
1068
|
<td align="right" class="linecount coveredLine"><pre>1</pre></td>
|
|
1069
|
<td align="left" class="src coveredLine"><pre> cacheControlRegister = (cacheControlRegister | 0x10000);</pre></td>
|
|
1070
|
</tr>
|
|
1071
|
|
|
1072
|
<tr>
|
|
1073
|
<td align="right" class="lineno"><pre>111</pre></td>
|
|
1074
|
<td align="right" class="linebranch"></td>
|
|
1075
|
<td align="right" class="linecount coveredLine"><pre>1</pre></td>
|
|
1076
|
<td align="left" class="src coveredLine"><pre> CCR_setValue(cacheControlRegister);</pre></td>
|
|
1077
|
</tr>
|
|
1078
|
|
|
1079
|
<tr>
|
|
1080
|
<td align="right" class="lineno"><pre>112</pre></td>
|
|
1081
|
<td align="right" class="linebranch"></td>
|
|
1082
|
<td align="right" class="linecount coveredLine"><pre>1</pre></td>
|
|
1083
|
<td align="left" class="src coveredLine"><pre>}</pre></td>
|
|
1084
|
</tr>
|
|
1085
|
|
|
1086
|
<tr>
|
|
1087
|
<td align="right" class="lineno"><pre>113</pre></td>
|
|
1088
|
<td align="right" class="linebranch"></td>
|
|
1089
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1090
|
<td align="left" class="src "><pre></pre></td>
|
|
1091
|
</tr>
|
|
1092
|
|
|
1093
|
<tr>
|
|
1094
|
<td align="right" class="lineno"><pre>114</pre></td>
|
|
1095
|
<td align="right" class="linebranch"></td>
|
|
1096
|
<td align="right" class="linecount uncoveredLine"><pre></pre></td>
|
|
1097
|
<td align="left" class="src uncoveredLine"><pre>void CCR_getInstructionAndDataErrorCounters( unsigned int* instructionErrorCounter, unsigned int* dataErrorCounter )</pre></td>
|
|
1098
|
</tr>
|
|
1099
|
|
|
1100
|
<tr>
|
|
1101
|
<td align="right" class="lineno"><pre>115</pre></td>
|
|
1102
|
<td align="right" class="linebranch"></td>
|
|
1103
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1104
|
<td align="left" class="src "><pre>{</pre></td>
|
|
1105
|
</tr>
|
|
1106
|
|
|
1107
|
<tr>
|
|
1108
|
<td align="right" class="lineno"><pre>116</pre></td>
|
|
1109
|
<td align="right" class="linebranch"></td>
|
|
1110
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1111
|
<td align="left" class="src "><pre> // [13:12] Instruction Tag Errors (ITE) - Number of detected parity errors in the instruction tag cache.</pre></td>
|
|
1112
|
</tr>
|
|
1113
|
|
|
1114
|
<tr>
|
|
1115
|
<td align="right" class="lineno"><pre>117</pre></td>
|
|
1116
|
<td align="right" class="linebranch"></td>
|
|
1117
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1118
|
<td align="left" class="src "><pre> // Only available if fault-tolerance is enabled (FT field in this register is non-zero).</pre></td>
|
|
1119
|
</tr>
|
|
1120
|
|
|
1121
|
<tr>
|
|
1122
|
<td align="right" class="lineno"><pre>118</pre></td>
|
|
1123
|
<td align="right" class="linebranch"></td>
|
|
1124
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1125
|
<td align="left" class="src "><pre> // [11:10] Instruction Data Errors (IDE) - Number of detected parity errors in the instruction data cache.</pre></td>
|
|
1126
|
</tr>
|
|
1127
|
|
|
1128
|
<tr>
|
|
1129
|
<td align="right" class="lineno"><pre>119</pre></td>
|
|
1130
|
<td align="right" class="linebranch"></td>
|
|
1131
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1132
|
<td align="left" class="src "><pre> // Only available if fault-tolerance is enabled (FT field in this register is non-zero).</pre></td>
|
|
1133
|
</tr>
|
|
1134
|
|
|
1135
|
<tr>
|
|
1136
|
<td align="right" class="lineno"><pre>120</pre></td>
|
|
1137
|
<td align="right" class="linebranch"></td>
|
|
1138
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1139
|
<td align="left" class="src "><pre></pre></td>
|
|
1140
|
</tr>
|
|
1141
|
|
|
1142
|
<tr>
|
|
1143
|
<td align="right" class="lineno"><pre>121</pre></td>
|
|
1144
|
<td align="right" class="linebranch"></td>
|
|
1145
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1146
|
<td align="left" class="src "><pre> unsigned int cacheControlRegister;</pre></td>
|
|
1147
|
</tr>
|
|
1148
|
|
|
1149
|
<tr>
|
|
1150
|
<td align="right" class="lineno"><pre>122</pre></td>
|
|
1151
|
<td align="right" class="linebranch"></td>
|
|
1152
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1153
|
<td align="left" class="src "><pre> unsigned int iTE;</pre></td>
|
|
1154
|
</tr>
|
|
1155
|
|
|
1156
|
<tr>
|
|
1157
|
<td align="right" class="lineno"><pre>123</pre></td>
|
|
1158
|
<td align="right" class="linebranch"></td>
|
|
1159
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1160
|
<td align="left" class="src "><pre> unsigned int iDE;</pre></td>
|
|
1161
|
</tr>
|
|
1162
|
|
|
1163
|
<tr>
|
|
1164
|
<td align="right" class="lineno"><pre>124</pre></td>
|
|
1165
|
<td align="right" class="linebranch"></td>
|
|
1166
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1167
|
<td align="left" class="src "><pre> unsigned int dTE;</pre></td>
|
|
1168
|
</tr>
|
|
1169
|
|
|
1170
|
<tr>
|
|
1171
|
<td align="right" class="lineno"><pre>125</pre></td>
|
|
1172
|
<td align="right" class="linebranch"></td>
|
|
1173
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1174
|
<td align="left" class="src "><pre> unsigned int dDE;</pre></td>
|
|
1175
|
</tr>
|
|
1176
|
|
|
1177
|
<tr>
|
|
1178
|
<td align="right" class="lineno"><pre>126</pre></td>
|
|
1179
|
<td align="right" class="linebranch"></td>
|
|
1180
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1181
|
<td align="left" class="src "><pre></pre></td>
|
|
1182
|
</tr>
|
|
1183
|
|
|
1184
|
<tr>
|
|
1185
|
<td align="right" class="lineno"><pre>127</pre></td>
|
|
1186
|
<td align="right" class="linebranch"></td>
|
|
1187
|
<td align="right" class="linecount uncoveredLine"><pre></pre></td>
|
|
1188
|
<td align="left" class="src uncoveredLine"><pre> cacheControlRegister = CCR_getValue();</pre></td>
|
|
1189
|
</tr>
|
|
1190
|
|
|
1191
|
<tr>
|
|
1192
|
<td align="right" class="lineno"><pre>128</pre></td>
|
|
1193
|
<td align="right" class="linebranch"></td>
|
|
1194
|
<td align="right" class="linecount uncoveredLine"><pre></pre></td>
|
|
1195
|
<td align="left" class="src uncoveredLine"><pre> iTE = (cacheControlRegister & COUNTER_FIELD_ITE) >> POS_ITE;</pre></td>
|
|
1196
|
</tr>
|
|
1197
|
|
|
1198
|
<tr>
|
|
1199
|
<td align="right" class="lineno"><pre>129</pre></td>
|
|
1200
|
<td align="right" class="linebranch"></td>
|
|
1201
|
<td align="right" class="linecount uncoveredLine"><pre></pre></td>
|
|
1202
|
<td align="left" class="src uncoveredLine"><pre> iDE = (cacheControlRegister & COUNTER_FIELD_IDE) >> POS_IDE;</pre></td>
|
|
1203
|
</tr>
|
|
1204
|
|
|
1205
|
<tr>
|
|
1206
|
<td align="right" class="lineno"><pre>130</pre></td>
|
|
1207
|
<td align="right" class="linebranch"></td>
|
|
1208
|
<td align="right" class="linecount uncoveredLine"><pre></pre></td>
|
|
1209
|
<td align="left" class="src uncoveredLine"><pre> dTE = (cacheControlRegister & COUNTER_FIELD_DTE) >> POS_DTE;</pre></td>
|
|
1210
|
</tr>
|
|
1211
|
|
|
1212
|
<tr>
|
|
1213
|
<td align="right" class="lineno"><pre>131</pre></td>
|
|
1214
|
<td align="right" class="linebranch"></td>
|
|
1215
|
<td align="right" class="linecount uncoveredLine"><pre></pre></td>
|
|
1216
|
<td align="left" class="src uncoveredLine"><pre> dDE = (cacheControlRegister & COUNTER_FIELD_DDE) >> POS_DDE;</pre></td>
|
|
1217
|
</tr>
|
|
1218
|
|
|
1219
|
<tr>
|
|
1220
|
<td align="right" class="lineno"><pre>132</pre></td>
|
|
1221
|
<td align="right" class="linebranch"></td>
|
|
1222
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1223
|
<td align="left" class="src "><pre></pre></td>
|
|
1224
|
</tr>
|
|
1225
|
|
|
1226
|
<tr>
|
|
1227
|
<td align="right" class="lineno"><pre>133</pre></td>
|
|
1228
|
<td align="right" class="linebranch"></td>
|
|
1229
|
<td align="right" class="linecount uncoveredLine"><pre></pre></td>
|
|
1230
|
<td align="left" class="src uncoveredLine"><pre> *instructionErrorCounter = iTE + iDE;</pre></td>
|
|
1231
|
</tr>
|
|
1232
|
|
|
1233
|
<tr>
|
|
1234
|
<td align="right" class="lineno"><pre>134</pre></td>
|
|
1235
|
<td align="right" class="linebranch"></td>
|
|
1236
|
<td align="right" class="linecount uncoveredLine"><pre></pre></td>
|
|
1237
|
<td align="left" class="src uncoveredLine"><pre> *dataErrorCounter = dTE + dDE;</pre></td>
|
|
1238
|
</tr>
|
|
1239
|
|
|
1240
|
<tr>
|
|
1241
|
<td align="right" class="lineno"><pre>135</pre></td>
|
|
1242
|
<td align="right" class="linebranch"></td>
|
|
1243
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1244
|
<td align="left" class="src "><pre></pre></td>
|
|
1245
|
</tr>
|
|
1246
|
|
|
1247
|
<tr>
|
|
1248
|
<td align="right" class="lineno"><pre>136</pre></td>
|
|
1249
|
<td align="right" class="linebranch"></td>
|
|
1250
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1251
|
<td align="left" class="src "><pre> // reset counters</pre></td>
|
|
1252
|
</tr>
|
|
1253
|
|
|
1254
|
<tr>
|
|
1255
|
<td align="right" class="lineno"><pre>137</pre></td>
|
|
1256
|
<td align="right" class="linebranch"></td>
|
|
1257
|
<td align="right" class="linecount uncoveredLine"><pre></pre></td>
|
|
1258
|
<td align="left" class="src uncoveredLine"><pre> cacheControlRegister = cacheControlRegister</pre></td>
|
|
1259
|
</tr>
|
|
1260
|
|
|
1261
|
<tr>
|
|
1262
|
<td align="right" class="lineno"><pre>138</pre></td>
|
|
1263
|
<td align="right" class="linebranch"></td>
|
|
1264
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1265
|
<td align="left" class="src "><pre> & COUNTER_FIELD_ITE</pre></td>
|
|
1266
|
</tr>
|
|
1267
|
|
|
1268
|
<tr>
|
|
1269
|
<td align="right" class="lineno"><pre>139</pre></td>
|
|
1270
|
<td align="right" class="linebranch"></td>
|
|
1271
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1272
|
<td align="left" class="src "><pre> & COUNTER_FIELD_IDE</pre></td>
|
|
1273
|
</tr>
|
|
1274
|
|
|
1275
|
<tr>
|
|
1276
|
<td align="right" class="lineno"><pre>140</pre></td>
|
|
1277
|
<td align="right" class="linebranch"></td>
|
|
1278
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1279
|
<td align="left" class="src "><pre> & COUNTER_FIELD_DTE</pre></td>
|
|
1280
|
</tr>
|
|
1281
|
|
|
1282
|
<tr>
|
|
1283
|
<td align="right" class="lineno"><pre>141</pre></td>
|
|
1284
|
<td align="right" class="linebranch"></td>
|
|
1285
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1286
|
<td align="left" class="src "><pre> & COUNTER_FIELD_DDE;</pre></td>
|
|
1287
|
</tr>
|
|
1288
|
|
|
1289
|
<tr>
|
|
1290
|
<td align="right" class="lineno"><pre>142</pre></td>
|
|
1291
|
<td align="right" class="linebranch"></td>
|
|
1292
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1293
|
<td align="left" class="src "><pre></pre></td>
|
|
1294
|
</tr>
|
|
1295
|
|
|
1296
|
<tr>
|
|
1297
|
<td align="right" class="lineno"><pre>143</pre></td>
|
|
1298
|
<td align="right" class="linebranch"></td>
|
|
1299
|
<td align="right" class="linecount uncoveredLine"><pre></pre></td>
|
|
1300
|
<td align="left" class="src uncoveredLine"><pre> CCR_setValue(cacheControlRegister);</pre></td>
|
|
1301
|
</tr>
|
|
1302
|
|
|
1303
|
<tr>
|
|
1304
|
<td align="right" class="lineno"><pre>144</pre></td>
|
|
1305
|
<td align="right" class="linebranch"></td>
|
|
1306
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1307
|
<td align="left" class="src "><pre>}</pre></td>
|
|
1308
|
</tr>
|
|
1309
|
|
|
1310
|
<tr>
|
|
1311
|
<td align="right" class="lineno"><pre>145</pre></td>
|
|
1312
|
<td align="right" class="linebranch"></td>
|
|
1313
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1314
|
<td align="left" class="src "><pre></pre></td>
|
|
1315
|
</tr>
|
|
1316
|
|
|
1317
|
<tr>
|
|
1318
|
<td align="right" class="lineno"><pre>146</pre></td>
|
|
1319
|
<td align="right" class="linebranch"></td>
|
|
1320
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1321
|
<td align="left" class="src "><pre>//*******************************************</pre></td>
|
|
1322
|
</tr>
|
|
1323
|
|
|
1324
|
<tr>
|
|
1325
|
<td align="right" class="lineno"><pre>147</pre></td>
|
|
1326
|
<td align="right" class="linebranch"></td>
|
|
1327
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1328
|
<td align="left" class="src "><pre>// ASR16 Register protection control register</pre></td>
|
|
1329
|
</tr>
|
|
1330
|
|
|
1331
|
<tr>
|
|
1332
|
<td align="right" class="lineno"><pre>148</pre></td>
|
|
1333
|
<td align="right" class="linebranch"></td>
|
|
1334
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1335
|
<td align="left" class="src "><pre></pre></td>
|
|
1336
|
</tr>
|
|
1337
|
|
|
1338
|
<tr>
|
|
1339
|
<td align="right" class="lineno"><pre>149</pre></td>
|
|
1340
|
<td align="right" class="linebranch"></td>
|
|
1341
|
<td align="right" class="linecount coveredLine"><pre>1</pre></td>
|
|
1342
|
<td align="left" class="src coveredLine"><pre>static void ASR16_resetRegisterProtectionControlRegister()</pre></td>
|
|
1343
|
</tr>
|
|
1344
|
|
|
1345
|
<tr>
|
|
1346
|
<td align="right" class="lineno"><pre>150</pre></td>
|
|
1347
|
<td align="right" class="linebranch"></td>
|
|
1348
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1349
|
<td align="left" class="src "><pre>{</pre></td>
|
|
1350
|
</tr>
|
|
1351
|
|
|
1352
|
<tr>
|
|
1353
|
<td align="right" class="lineno"><pre>151</pre></td>
|
|
1354
|
<td align="right" class="linebranch"></td>
|
|
1355
|
<td align="right" class="linecount coveredLine"><pre>1</pre></td>
|
|
1356
|
<td align="left" class="src coveredLine"><pre> *asr16Ptr = 0x00;</pre></td>
|
|
1357
|
</tr>
|
|
1358
|
|
|
1359
|
<tr>
|
|
1360
|
<td align="right" class="lineno"><pre>152</pre></td>
|
|
1361
|
<td align="right" class="linebranch"></td>
|
|
1362
|
<td align="right" class="linecount coveredLine"><pre>1</pre></td>
|
|
1363
|
<td align="left" class="src coveredLine"><pre>}</pre></td>
|
|
1364
|
</tr>
|
|
1365
|
|
|
1366
|
<tr>
|
|
1367
|
<td align="right" class="lineno"><pre>153</pre></td>
|
|
1368
|
<td align="right" class="linebranch"></td>
|
|
1369
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1370
|
<td align="left" class="src "><pre></pre></td>
|
|
1371
|
</tr>
|
|
1372
|
|
|
1373
|
<tr>
|
|
1374
|
<td align="right" class="lineno"><pre>154</pre></td>
|
|
1375
|
<td align="right" class="linebranch"></td>
|
|
1376
|
<td align="right" class="linecount uncoveredLine"><pre></pre></td>
|
|
1377
|
<td align="left" class="src uncoveredLine"><pre>void ASR16_get_FPRF_IURF_ErrorCounters( unsigned int* fprfErrorCounter, unsigned int* iurfErrorCounter)</pre></td>
|
|
1378
|
</tr>
|
|
1379
|
|
|
1380
|
<tr>
|
|
1381
|
<td align="right" class="lineno"><pre>155</pre></td>
|
|
1382
|
<td align="right" class="linebranch"></td>
|
|
1383
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1384
|
<td align="left" class="src "><pre>{</pre></td>
|
|
1385
|
</tr>
|
|
1386
|
|
|
1387
|
<tr>
|
|
1388
|
<td align="right" class="lineno"><pre>156</pre></td>
|
|
1389
|
<td align="right" class="linebranch"></td>
|
|
1390
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1391
|
<td align="left" class="src "><pre> /** This function is used to retrieve the integer unit register file error counter and the floating point unit</pre></td>
|
|
1392
|
</tr>
|
|
1393
|
|
|
1394
|
<tr>
|
|
1395
|
<td align="right" class="lineno"><pre>157</pre></td>
|
|
1396
|
<td align="right" class="linebranch"></td>
|
|
1397
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1398
|
<td align="left" class="src "><pre> * register file error counter</pre></td>
|
|
1399
|
</tr>
|
|
1400
|
|
|
1401
|
<tr>
|
|
1402
|
<td align="right" class="lineno"><pre>158</pre></td>
|
|
1403
|
<td align="right" class="linebranch"></td>
|
|
1404
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1405
|
<td align="left" class="src "><pre> *</pre></td>
|
|
1406
|
</tr>
|
|
1407
|
|
|
1408
|
<tr>
|
|
1409
|
<td align="right" class="lineno"><pre>159</pre></td>
|
|
1410
|
<td align="right" class="linebranch"></td>
|
|
1411
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1412
|
<td align="left" class="src "><pre> * @return void</pre></td>
|
|
1413
|
</tr>
|
|
1414
|
|
|
1415
|
<tr>
|
|
1416
|
<td align="right" class="lineno"><pre>160</pre></td>
|
|
1417
|
<td align="right" class="linebranch"></td>
|
|
1418
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1419
|
<td align="left" class="src "><pre> *</pre></td>
|
|
1420
|
</tr>
|
|
1421
|
|
|
1422
|
<tr>
|
|
1423
|
<td align="right" class="lineno"><pre>161</pre></td>
|
|
1424
|
<td align="right" class="linebranch"></td>
|
|
1425
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1426
|
<td align="left" class="src "><pre> * [29:27] FP RF error counter - Number of detected parity errors in the FP register file.</pre></td>
|
|
1427
|
</tr>
|
|
1428
|
|
|
1429
|
<tr>
|
|
1430
|
<td align="right" class="lineno"><pre>162</pre></td>
|
|
1431
|
<td align="right" class="linebranch"></td>
|
|
1432
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1433
|
<td align="left" class="src "><pre> * [13:11] IU RF error counter - Number of detected parity errors in the IU register file.</pre></td>
|
|
1434
|
</tr>
|
|
1435
|
|
|
1436
|
<tr>
|
|
1437
|
<td align="right" class="lineno"><pre>163</pre></td>
|
|
1438
|
<td align="right" class="linebranch"></td>
|
|
1439
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1440
|
<td align="left" class="src "><pre> *</pre></td>
|
|
1441
|
</tr>
|
|
1442
|
|
|
1443
|
<tr>
|
|
1444
|
<td align="right" class="lineno"><pre>164</pre></td>
|
|
1445
|
<td align="right" class="linebranch"></td>
|
|
1446
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1447
|
<td align="left" class="src "><pre> */</pre></td>
|
|
1448
|
</tr>
|
|
1449
|
|
|
1450
|
<tr>
|
|
1451
|
<td align="right" class="lineno"><pre>165</pre></td>
|
|
1452
|
<td align="right" class="linebranch"></td>
|
|
1453
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1454
|
<td align="left" class="src "><pre></pre></td>
|
|
1455
|
</tr>
|
|
1456
|
|
|
1457
|
<tr>
|
|
1458
|
<td align="right" class="lineno"><pre>166</pre></td>
|
|
1459
|
<td align="right" class="linebranch"></td>
|
|
1460
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1461
|
<td align="left" class="src "><pre> unsigned int asr16;</pre></td>
|
|
1462
|
</tr>
|
|
1463
|
|
|
1464
|
<tr>
|
|
1465
|
<td align="right" class="lineno"><pre>167</pre></td>
|
|
1466
|
<td align="right" class="linebranch"></td>
|
|
1467
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1468
|
<td align="left" class="src "><pre></pre></td>
|
|
1469
|
</tr>
|
|
1470
|
|
|
1471
|
<tr>
|
|
1472
|
<td align="right" class="lineno"><pre>168</pre></td>
|
|
1473
|
<td align="right" class="linebranch"></td>
|
|
1474
|
<td align="right" class="linecount uncoveredLine"><pre></pre></td>
|
|
1475
|
<td align="left" class="src uncoveredLine"><pre> asr16 = *asr16Ptr;</pre></td>
|
|
1476
|
</tr>
|
|
1477
|
|
|
1478
|
<tr>
|
|
1479
|
<td align="right" class="lineno"><pre>169</pre></td>
|
|
1480
|
<td align="right" class="linebranch"></td>
|
|
1481
|
<td align="right" class="linecount uncoveredLine"><pre></pre></td>
|
|
1482
|
<td align="left" class="src uncoveredLine"><pre> *fprfErrorCounter = ( asr16 & COUNTER_FIELD_FPRF ) >> POS_FPRF;</pre></td>
|
|
1483
|
</tr>
|
|
1484
|
|
|
1485
|
<tr>
|
|
1486
|
<td align="right" class="lineno"><pre>170</pre></td>
|
|
1487
|
<td align="right" class="linebranch"></td>
|
|
1488
|
<td align="right" class="linecount uncoveredLine"><pre></pre></td>
|
|
1489
|
<td align="left" class="src uncoveredLine"><pre> *iurfErrorCounter = ( asr16 & COUNTER_FIELD_IURF ) >> POS_IURF;</pre></td>
|
|
1490
|
</tr>
|
|
1491
|
|
|
1492
|
<tr>
|
|
1493
|
<td align="right" class="lineno"><pre>171</pre></td>
|
|
1494
|
<td align="right" class="linebranch"></td>
|
|
1495
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1496
|
<td align="left" class="src "><pre></pre></td>
|
|
1497
|
</tr>
|
|
1498
|
|
|
1499
|
<tr>
|
|
1500
|
<td align="right" class="lineno"><pre>172</pre></td>
|
|
1501
|
<td align="right" class="linebranch"></td>
|
|
1502
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1503
|
<td align="left" class="src "><pre> // reset the counter to 0</pre></td>
|
|
1504
|
</tr>
|
|
1505
|
|
|
1506
|
<tr>
|
|
1507
|
<td align="right" class="lineno"><pre>173</pre></td>
|
|
1508
|
<td align="right" class="linebranch"></td>
|
|
1509
|
<td align="right" class="linecount uncoveredLine"><pre></pre></td>
|
|
1510
|
<td align="left" class="src uncoveredLine"><pre> asr16 = asr16</pre></td>
|
|
1511
|
</tr>
|
|
1512
|
|
|
1513
|
<tr>
|
|
1514
|
<td align="right" class="lineno"><pre>174</pre></td>
|
|
1515
|
<td align="right" class="linebranch"></td>
|
|
1516
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1517
|
<td align="left" class="src "><pre> & COUNTER_MASK_FPRF</pre></td>
|
|
1518
|
</tr>
|
|
1519
|
|
|
1520
|
<tr>
|
|
1521
|
<td align="right" class="lineno"><pre>175</pre></td>
|
|
1522
|
<td align="right" class="linebranch"></td>
|
|
1523
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1524
|
<td align="left" class="src "><pre> & COUNTER_FIELD_IURF;</pre></td>
|
|
1525
|
</tr>
|
|
1526
|
|
|
1527
|
<tr>
|
|
1528
|
<td align="right" class="lineno"><pre>176</pre></td>
|
|
1529
|
<td align="right" class="linebranch"></td>
|
|
1530
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1531
|
<td align="left" class="src "><pre></pre></td>
|
|
1532
|
</tr>
|
|
1533
|
|
|
1534
|
<tr>
|
|
1535
|
<td align="right" class="lineno"><pre>177</pre></td>
|
|
1536
|
<td align="right" class="linebranch"></td>
|
|
1537
|
<td align="right" class="linecount uncoveredLine"><pre></pre></td>
|
|
1538
|
<td align="left" class="src uncoveredLine"><pre> *asr16Ptr = asr16;</pre></td>
|
|
1539
|
</tr>
|
|
1540
|
|
|
1541
|
<tr>
|
|
1542
|
<td align="right" class="lineno"><pre>178</pre></td>
|
|
1543
|
<td align="right" class="linebranch"></td>
|
|
1544
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1545
|
<td align="left" class="src "><pre>}</pre></td>
|
|
1546
|
</tr>
|
|
1547
|
|
|
1548
|
<tr>
|
|
1549
|
<td align="right" class="lineno"><pre>179</pre></td>
|
|
1550
|
<td align="right" class="linebranch"></td>
|
|
1551
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1552
|
<td align="left" class="src "><pre></pre></td>
|
|
1553
|
</tr>
|
|
1554
|
|
|
1555
|
<tr>
|
|
1556
|
<td align="right" class="lineno"><pre>180</pre></td>
|
|
1557
|
<td align="right" class="linebranch"></td>
|
|
1558
|
<td align="right" class="linecount coveredLine"><pre>1</pre></td>
|
|
1559
|
<td align="left" class="src coveredLine"><pre>static void faultTolerantScheme()</pre></td>
|
|
1560
|
</tr>
|
|
1561
|
|
|
1562
|
<tr>
|
|
1563
|
<td align="right" class="lineno"><pre>181</pre></td>
|
|
1564
|
<td align="right" class="linebranch"></td>
|
|
1565
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1566
|
<td align="left" class="src "><pre>{</pre></td>
|
|
1567
|
</tr>
|
|
1568
|
|
|
1569
|
<tr>
|
|
1570
|
<td align="right" class="lineno"><pre>182</pre></td>
|
|
1571
|
<td align="right" class="linebranch"></td>
|
|
1572
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1573
|
<td align="left" class="src "><pre> // [20:19] FT scheme (FT) - “00” = no FT, “01” = 4-bit checking implemented</pre></td>
|
|
1574
|
</tr>
|
|
1575
|
|
|
1576
|
<tr>
|
|
1577
|
<td align="right" class="lineno"><pre>183</pre></td>
|
|
1578
|
<td align="right" class="linebranch"></td>
|
|
1579
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1580
|
<td align="left" class="src "><pre> unsigned int cacheControlRegister;</pre></td>
|
|
1581
|
</tr>
|
|
1582
|
|
|
1583
|
<tr>
|
|
1584
|
<td align="right" class="lineno"><pre>184</pre></td>
|
|
1585
|
<td align="right" class="linebranch"></td>
|
|
1586
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1587
|
<td align="left" class="src "><pre> unsigned int *plugAndPlayRegister;</pre></td>
|
|
1588
|
</tr>
|
|
1589
|
|
|
1590
|
<tr>
|
|
1591
|
<td align="right" class="lineno"><pre>185</pre></td>
|
|
1592
|
<td align="right" class="linebranch"></td>
|
|
1593
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1594
|
<td align="left" class="src "><pre> unsigned int vendorId;</pre></td>
|
|
1595
|
</tr>
|
|
1596
|
|
|
1597
|
<tr>
|
|
1598
|
<td align="right" class="lineno"><pre>186</pre></td>
|
|
1599
|
<td align="right" class="linebranch"></td>
|
|
1600
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1601
|
<td align="left" class="src "><pre> unsigned int deviceId;</pre></td>
|
|
1602
|
</tr>
|
|
1603
|
|
|
1604
|
<tr>
|
|
1605
|
<td align="right" class="lineno"><pre>187</pre></td>
|
|
1606
|
<td align="right" class="linebranch"></td>
|
|
1607
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1608
|
<td align="left" class="src "><pre></pre></td>
|
|
1609
|
</tr>
|
|
1610
|
|
|
1611
|
<tr>
|
|
1612
|
<td align="right" class="lineno"><pre>188</pre></td>
|
|
1613
|
<td align="right" class="linebranch"></td>
|
|
1614
|
<td align="right" class="linecount coveredLine"><pre>1</pre></td>
|
|
1615
|
<td align="left" class="src coveredLine"><pre> plugAndPlayRegister = (unsigned int*) REGS_ADDR_PLUGANDPLAY;</pre></td>
|
|
1616
|
</tr>
|
|
1617
|
|
|
1618
|
<tr>
|
|
1619
|
<td align="right" class="lineno"><pre>189</pre></td>
|
|
1620
|
<td align="right" class="linebranch"></td>
|
|
1621
|
<td align="right" class="linecount coveredLine"><pre>1</pre></td>
|
|
1622
|
<td align="left" class="src coveredLine"><pre> vendorId = ( (*plugAndPlayRegister) & 0xff000000 ) >> 24;</pre></td>
|
|
1623
|
</tr>
|
|
1624
|
|
|
1625
|
<tr>
|
|
1626
|
<td align="right" class="lineno"><pre>190</pre></td>
|
|
1627
|
<td align="right" class="linebranch"></td>
|
|
1628
|
<td align="right" class="linecount coveredLine"><pre>1</pre></td>
|
|
1629
|
<td align="left" class="src coveredLine"><pre> deviceId = ( (*plugAndPlayRegister) & 0x00fff000 ) >> 12;</pre></td>
|
|
1630
|
</tr>
|
|
1631
|
|
|
1632
|
<tr>
|
|
1633
|
<td align="right" class="lineno"><pre>191</pre></td>
|
|
1634
|
<td align="right" class="linebranch"></td>
|
|
1635
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1636
|
<td align="left" class="src "><pre></pre></td>
|
|
1637
|
</tr>
|
|
1638
|
|
|
1639
|
<tr>
|
|
1640
|
<td align="right" class="lineno"><pre>192</pre></td>
|
|
1641
|
<td align="right" class="linebranch"></td>
|
|
1642
|
<td align="right" class="linecount coveredLine"><pre>1</pre></td>
|
|
1643
|
<td align="left" class="src coveredLine"><pre> cacheControlRegister = CCR_getValue();</pre></td>
|
|
1644
|
</tr>
|
|
1645
|
|
|
1646
|
<tr>
|
|
1647
|
<td align="right" class="lineno"><pre>193</pre></td>
|
|
1648
|
<td align="right" class="linebranch"></td>
|
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1649
|
<td align="right" class="linecount "><pre></pre></td>
|
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1650
|
<td align="left" class="src "><pre></pre></td>
|
|
1651
|
</tr>
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1652
|
|
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1653
|
<tr>
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1654
|
<td align="right" class="lineno"><pre>194</pre></td>
|
|
1655
|
<td align="right" class="linebranch"></td>
|
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1656
|
<td align="right" class="linecount coveredLine"><pre>1</pre></td>
|
|
1657
|
<td align="left" class="src coveredLine"><pre> if( (vendorId == VENDORID_GAISLER) & (deviceId ==DEVICEID_LEON3FT) )</pre></td>
|
|
1658
|
</tr>
|
|
1659
|
|
|
1660
|
<tr>
|
|
1661
|
<td align="right" class="lineno"><pre>195</pre></td>
|
|
1662
|
<td align="right" class="linebranch"></td>
|
|
1663
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1664
|
<td align="left" class="src "><pre> {</pre></td>
|
|
1665
|
</tr>
|
|
1666
|
|
|
1667
|
<tr>
|
|
1668
|
<td align="right" class="lineno"><pre>196</pre></td>
|
|
1669
|
<td align="right" class="linebranch"></td>
|
|
1670
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1671
|
<td align="left" class="src "><pre> PRINTF("in faultTolerantScheme *** Leon3FT detected\n");</pre></td>
|
|
1672
|
</tr>
|
|
1673
|
|
|
1674
|
<tr>
|
|
1675
|
<td align="right" class="lineno"><pre>197</pre></td>
|
|
1676
|
<td align="right" class="linebranch"></td>
|
|
1677
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1678
|
<td align="left" class="src "><pre> PRINTF2(" *** vendorID = 0x%x, deviceId = 0x%x\n", vendorId, deviceId);</pre></td>
|
|
1679
|
</tr>
|
|
1680
|
|
|
1681
|
<tr>
|
|
1682
|
<td align="right" class="lineno"><pre>198</pre></td>
|
|
1683
|
<td align="right" class="linebranch"></td>
|
|
1684
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1685
|
<td align="left" class="src "><pre> PRINTF1("ASR16 IU RF protection, bit 0 (IDI) is: 0x%x (0 => protection enabled)\n",</pre></td>
|
|
1686
|
</tr>
|
|
1687
|
|
|
1688
|
<tr>
|
|
1689
|
<td align="right" class="lineno"><pre>199</pre></td>
|
|
1690
|
<td align="right" class="linebranch"></td>
|
|
1691
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1692
|
<td align="left" class="src "><pre> (*asr16Ptr >> POS_IDI) & 1);</pre></td>
|
|
1693
|
</tr>
|
|
1694
|
|
|
1695
|
<tr>
|
|
1696
|
<td align="right" class="lineno"><pre>200</pre></td>
|
|
1697
|
<td align="right" class="linebranch"></td>
|
|
1698
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1699
|
<td align="left" class="src "><pre> PRINTF1("ASR16 FP RF protection, bit 16 (FDI) is: 0x%x (0 => protection enabled)\n",</pre></td>
|
|
1700
|
</tr>
|
|
1701
|
|
|
1702
|
<tr>
|
|
1703
|
<td align="right" class="lineno"><pre>201</pre></td>
|
|
1704
|
<td align="right" class="linebranch"></td>
|
|
1705
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1706
|
<td align="left" class="src "><pre> (*asr16Ptr >> POS_FDI) & 1);</pre></td>
|
|
1707
|
</tr>
|
|
1708
|
|
|
1709
|
<tr>
|
|
1710
|
<td align="right" class="lineno"><pre>202</pre></td>
|
|
1711
|
<td align="right" class="linebranch"></td>
|
|
1712
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1713
|
<td align="left" class="src "><pre> PRINTF1("ASR16 IU FT ID bits [15:14] is: 0x%x (2 => 8-bit parity without restart)\n",</pre></td>
|
|
1714
|
</tr>
|
|
1715
|
|
|
1716
|
<tr>
|
|
1717
|
<td align="right" class="lineno"><pre>203</pre></td>
|
|
1718
|
<td align="right" class="linebranch"></td>
|
|
1719
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1720
|
<td align="left" class="src "><pre> (*asr16Ptr >> POS_IUFTID) & 0x3);</pre></td>
|
|
1721
|
</tr>
|
|
1722
|
|
|
1723
|
<tr>
|
|
1724
|
<td align="right" class="lineno"><pre>204</pre></td>
|
|
1725
|
<td align="right" class="linebranch"></td>
|
|
1726
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1727
|
<td align="left" class="src "><pre> PRINTF1("ASR16 FP FT ID bits [31:30] is: 0x%x (1 => 4-bit parity with restart)\n",</pre></td>
|
|
1728
|
</tr>
|
|
1729
|
|
|
1730
|
<tr>
|
|
1731
|
<td align="right" class="lineno"><pre>205</pre></td>
|
|
1732
|
<td align="right" class="linebranch"></td>
|
|
1733
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1734
|
<td align="left" class="src "><pre> (*asr16Ptr >> POS_FPFTID) & 0x03);</pre></td>
|
|
1735
|
</tr>
|
|
1736
|
|
|
1737
|
<tr>
|
|
1738
|
<td align="right" class="lineno"><pre>206</pre></td>
|
|
1739
|
<td align="right" class="linebranch"></td>
|
|
1740
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1741
|
<td align="left" class="src "><pre> PRINTF1("CCR FT bits [20:19] are: 0x%x (1 => 4-bit parity with restart)\n",</pre></td>
|
|
1742
|
</tr>
|
|
1743
|
|
|
1744
|
<tr>
|
|
1745
|
<td align="right" class="lineno"><pre>207</pre></td>
|
|
1746
|
<td align="right" class="linebranch"></td>
|
|
1747
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1748
|
<td align="left" class="src "><pre> (cacheControlRegister >> POS_FT) & 0x3 );</pre></td>
|
|
1749
|
</tr>
|
|
1750
|
|
|
1751
|
<tr>
|
|
1752
|
<td align="right" class="lineno"><pre>208</pre></td>
|
|
1753
|
<td align="right" class="linebranch"></td>
|
|
1754
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1755
|
<td align="left" class="src "><pre></pre></td>
|
|
1756
|
</tr>
|
|
1757
|
|
|
1758
|
<tr>
|
|
1759
|
<td align="right" class="lineno"><pre>209</pre></td>
|
|
1760
|
<td align="right" class="linebranch"></td>
|
|
1761
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1762
|
<td align="left" class="src "><pre> // CCR The FFT bits are just read, the FT scheme is set to “01” = 4-bit checking implemented by default</pre></td>
|
|
1763
|
</tr>
|
|
1764
|
|
|
1765
|
<tr>
|
|
1766
|
<td align="right" class="lineno"><pre>210</pre></td>
|
|
1767
|
<td align="right" class="linebranch"></td>
|
|
1768
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1769
|
<td align="left" class="src "><pre></pre></td>
|
|
1770
|
</tr>
|
|
1771
|
|
|
1772
|
<tr>
|
|
1773
|
<td align="right" class="lineno"><pre>211</pre></td>
|
|
1774
|
<td align="right" class="linebranch"></td>
|
|
1775
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1776
|
<td align="left" class="src "><pre> // ASR16 Ancillary State Register configuration (Register protection control register)</pre></td>
|
|
1777
|
</tr>
|
|
1778
|
|
|
1779
|
<tr>
|
|
1780
|
<td align="right" class="lineno"><pre>212</pre></td>
|
|
1781
|
<td align="right" class="linebranch"></td>
|
|
1782
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1783
|
<td align="left" class="src "><pre> // IU RF protection is set by default, bit 0 IDI = 0</pre></td>
|
|
1784
|
</tr>
|
|
1785
|
|
|
1786
|
<tr>
|
|
1787
|
<td align="right" class="lineno"><pre>213</pre></td>
|
|
1788
|
<td align="right" class="linebranch"></td>
|
|
1789
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1790
|
<td align="left" class="src "><pre> // FP RF protection is set by default, bit 16 FDI = 0</pre></td>
|
|
1791
|
</tr>
|
|
1792
|
|
|
1793
|
<tr>
|
|
1794
|
<td align="right" class="lineno"><pre>214</pre></td>
|
|
1795
|
<td align="right" class="linebranch"></td>
|
|
1796
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1797
|
<td align="left" class="src "><pre> }</pre></td>
|
|
1798
|
</tr>
|
|
1799
|
|
|
1800
|
<tr>
|
|
1801
|
<td align="right" class="lineno"><pre>215</pre></td>
|
|
1802
|
<td align="right" class="linebranch"></td>
|
|
1803
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1804
|
<td align="left" class="src "><pre> else</pre></td>
|
|
1805
|
</tr>
|
|
1806
|
|
|
1807
|
<tr>
|
|
1808
|
<td align="right" class="lineno"><pre>216</pre></td>
|
|
1809
|
<td align="right" class="linebranch"></td>
|
|
1810
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1811
|
<td align="left" class="src "><pre> {</pre></td>
|
|
1812
|
</tr>
|
|
1813
|
|
|
1814
|
<tr>
|
|
1815
|
<td align="right" class="lineno"><pre>217</pre></td>
|
|
1816
|
<td align="right" class="linebranch"></td>
|
|
1817
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1818
|
<td align="left" class="src "><pre> PRINTF("in faultTolerantScheme *** Leon3FT not detected\n");</pre></td>
|
|
1819
|
</tr>
|
|
1820
|
|
|
1821
|
<tr>
|
|
1822
|
<td align="right" class="lineno"><pre>218</pre></td>
|
|
1823
|
<td align="right" class="linebranch"></td>
|
|
1824
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1825
|
<td align="left" class="src "><pre> PRINTF2(" *** vendorID = 0x%x, deviceId = 0x%x\n", vendorId, deviceId);</pre></td>
|
|
1826
|
</tr>
|
|
1827
|
|
|
1828
|
<tr>
|
|
1829
|
<td align="right" class="lineno"><pre>219</pre></td>
|
|
1830
|
<td align="right" class="linebranch"></td>
|
|
1831
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1832
|
<td align="left" class="src "><pre> }</pre></td>
|
|
1833
|
</tr>
|
|
1834
|
|
|
1835
|
<tr>
|
|
1836
|
<td align="right" class="lineno"><pre>220</pre></td>
|
|
1837
|
<td align="right" class="linebranch"></td>
|
|
1838
|
<td align="right" class="linecount coveredLine"><pre>1</pre></td>
|
|
1839
|
<td align="left" class="src coveredLine"><pre>}</pre></td>
|
|
1840
|
</tr>
|
|
1841
|
|
|
1842
|
<tr>
|
|
1843
|
<td align="right" class="lineno"><pre>221</pre></td>
|
|
1844
|
<td align="right" class="linebranch"></td>
|
|
1845
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1846
|
<td align="left" class="src "><pre></pre></td>
|
|
1847
|
</tr>
|
|
1848
|
|
|
1849
|
<tr>
|
|
1850
|
<td align="right" class="lineno"><pre>222</pre></td>
|
|
1851
|
<td align="right" class="linebranch"></td>
|
|
1852
|
<td align="right" class="linecount "><pre></pre></td>
|
|
1853
|
<td align="left" class="src "><pre>#endif /* GSCMEMORY_HPP_ */</pre></td>
|
|
1854
|
</tr>
|
|
1855
|
|
|
1856
|
</table>
|
|
1857
|
<br>
|
|
1858
|
|
|
1859
|
<table width="100%" border="0" cellspacing="0" cellpadding="0">
|
|
1860
|
<tr><td class="hr"><td></tr>
|
|
1861
|
<tr><td class="footer">Generated by: <a href="http://gcovr.com">GCOVR (Version 4.1)</a></td></tr>
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1862
|
</table>
|
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1863
|
<br>
|
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1864
|
|
|
1865
|
</body>
|
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1866
|
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1867
|
</html>
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1868
|
|